ARM: OMAP5: Enable support for AVS0 for OMAP5 production devices
[oweals/u-boot.git] / arch / arm / include / asm / arch-tegra20 / mc.h
1 /*
2  *  (C) Copyright 2014
3  *  NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #ifndef _TEGRA20_MC_H_
9 #define _TEGRA20_MC_H_
10
11 /**
12  * Defines the memory controller registers we need/care about
13  */
14 struct mc_ctlr {
15         u32 reserved0[3];                       /* offset 0x00 - 0x08 */
16         u32 mc_emem_cfg;                        /* offset 0x0C */
17         u32 mc_emem_adr_cfg;                    /* offset 0x10 */
18         u32 mc_emem_arb_cfg0;                   /* offset 0x14 */
19         u32 mc_emem_arb_cfg1;                   /* offset 0x18 */
20         u32 mc_emem_arb_cfg2;                   /* offset 0x1C */
21         u32 reserved1;                          /* offset 0x20 */
22         u32 mc_gart_cfg;                        /* offset 0x24 */
23         u32 mc_gart_entry_addr;                 /* offset 0x28 */
24         u32 mc_gart_entry_data;                 /* offset 0x2C */
25         u32 mc_gart_error_req;                  /* offset 0x30 */
26         u32 mc_gart_error_addr;                 /* offset 0x34 */
27         u32 reserved2;                          /* offset 0x38 */
28         u32 mc_timeout_ctrl;                    /* offset 0x3C */
29         u32 reserved3[6];                       /* offset 0x40 - 0x54 */
30         u32 mc_decerr_emem_others_status;       /* offset 0x58 */
31         u32 mc_decerr_emem_others_adr;          /* offset 0x5C */
32         u32 reserved4[40];                      /* offset 0x60 - 0xFC */
33         u32 reserved5[93];                      /* offset 0x100 - 0x270 */
34 };
35
36 #endif  /* _TEGRA20_MC_H_ */