3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __ASM_ARCH_TEGRA_DC_H
25 #define __ASM_ARCH_TEGRA_DC_H
27 /* Register definitions for the Tegra display controller */
29 /* CMD register 0x000 ~ 0x43 */
31 /* Address 0x000 ~ 0x002 */
32 uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */
33 uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
34 uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
36 uint reserved0[5]; /* reserved_0[5] */
38 /* Address 0x008 ~ 0x00a */
39 uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */
40 uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
41 uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
43 uint reserved1[5]; /* reserved_1[5] */
45 /* Address 0x010 ~ 0x012 */
46 uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */
47 uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
48 uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
50 uint reserved2[5]; /* reserved_2[5] */
52 /* Address 0x018 ~ 0x01a */
53 uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */
54 uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
55 uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
57 uint reserved3[13]; /* reserved_3[13] */
60 uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */
62 uint reserved4[7]; /* reserved_4[7] */
64 /* Address 0x030 ~ 0x033 */
65 uint ctxsw; /* _CMD_CTXSW_0 */
66 uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */
67 uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */
68 uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */
70 uint reserved5[2]; /* reserved_0[2] */
72 /* Address 0x036 ~ 0x03e */
73 uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */
74 uint int_stat; /* _CMD_INT_STATUS_0 */
75 uint int_mask; /* _CMD_INT_MASK_0 */
76 uint int_enb; /* _CMD_INT_ENABLE_0 */
77 uint int_type; /* _CMD_INT_TYPE_0 */
78 uint int_polarity; /* _CMD_INT_POLARITY_0 */
79 uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */
80 uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */
81 uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */
83 uint reserved6; /* reserved_6 */
85 /* Address 0x040 ~ 0x043 */
86 uint state_access; /* _CMD_STATE_ACCESS_0 */
87 uint state_ctrl; /* _CMD_STATE_CONTROL_0 */
88 uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */
89 uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */
94 PIN_OUTPUT_SEL_COUNT = 7,
97 /* COM register 0x300 ~ 0x329 */
99 /* Address 0x300 ~ 0x301 */
100 uint crc_ctrl; /* _COM_CRC_CONTROL_0 */
101 uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */
103 /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
104 uint pin_output_enb[PIN_REG_COUNT];
106 /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
107 uint pin_output_polarity[PIN_REG_COUNT];
109 /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
110 uint pin_output_data[PIN_REG_COUNT];
112 /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
113 uint pin_input_enb[PIN_REG_COUNT];
115 /* Address 0x312 ~ 0x313 */
116 uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */
117 uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */
119 /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
120 uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
122 /* Address 0x31b ~ 0x329 */
123 uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */
124 uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */
125 uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */
126 uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */
127 uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */
128 uint spi_ctrl; /* _COM_SPI_CONTROL_0 */
129 uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */
130 uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */
131 uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */
132 uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */
133 uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */
134 uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */
135 uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */
136 uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
137 uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */
140 enum dc_disp_h_pulse_pos {
145 H_PULSE0_POSITION_COUNT,
148 struct _disp_h_pulse {
149 /* _DISP_H_PULSE0/1/2_CONTROL_0 */
151 /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
152 uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
155 enum dc_disp_v_pulse_pos {
159 V_PULSE0_POSITION_COUNT,
162 struct _disp_v_pulse0 {
163 /* _DISP_H_PULSE0/1_CONTROL_0 */
165 /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
166 uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
169 struct _disp_v_pulse2 {
170 /* _DISP_H_PULSE2/3_CONTROL_0 */
172 /* _DISP_H_PULSE2/3_POSITION_A_0 */
176 enum dc_disp_h_pulse_reg {
183 enum dc_disp_pp_select {
191 /* DISP register 0x400 ~ 0x4c1 */
193 /* Address 0x400 ~ 0x40a */
194 uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
195 uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */
196 uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */
197 uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */
198 uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
199 uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */
200 uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */
201 uint sync_width; /* _DISP_SYNC_WIDTH_0 */
202 uint back_porch; /* _DISP_BACK_PORCH_0 */
203 uint disp_active; /* _DISP_DISP_ACTIVE_0 */
204 uint front_porch; /* _DISP_FRONT_PORCH_0 */
206 /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */
207 struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
209 /* Address 0x41a ~ 0x421 */
210 struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
211 struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
213 /* Address 0x422 ~ 0x425 */
214 struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
215 struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
217 /* Address 0x426 ~ 0x429 */
218 uint m0_ctrl; /* _DISP_M0_CONTROL_0 */
219 uint m1_ctrl; /* _DISP_M1_CONTROL_0 */
220 uint di_ctrl; /* _DISP_DI_CONTROL_0 */
221 uint pp_ctrl; /* _DISP_PP_CONTROL_0 */
223 /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
224 uint pp_select[PP_SELECT_COUNT];
226 /* Address 0x42e ~ 0x435 */
227 uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */
228 uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */
229 uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */
230 uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */
231 uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */
232 uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
233 uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */
234 uint border_color; /* _DISP_BORDER_COLOR_0 */
236 /* Address 0x436 ~ 0x439 */
237 uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */
238 uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */
239 uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */
240 uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */
242 uint reserved0[2]; /* reserved_0[2] */
244 /* Address 0x43c ~ 0x442 */
245 uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */
246 uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */
247 uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */
248 uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */
249 uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */
250 uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */
251 uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */
253 /* Address 0x442 ~ 0x446 */
254 uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
255 uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
256 uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
257 uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */
259 uint reserved1[0x39]; /* reserved1[0x39], */
261 /* Address 0x480 ~ 0x484 */
262 uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */
263 uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
264 uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
265 uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
266 uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */
268 uint reserved2[0x3b]; /* reserved2[0x3b] */
270 /* Address 0x4c0 ~ 0x4c1 */
271 uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */
272 uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */
275 enum dc_winc_filter_p {
276 WINC_FILTER_COUNT = 0x10,
279 /* Window A/B/C register 0x500 ~ 0x628 */
283 uint color_palette; /* _WINC_COLOR_PALETTE_0 */
285 uint reserved0[0xff]; /* reserved_0[0xff] */
288 uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */
290 /* _WINC_H_FILTER_P00~0F_0 */
291 /* Address 0x601 ~ 0x610 */
292 uint h_filter_p[WINC_FILTER_COUNT];
294 /* Address 0x611 ~ 0x618 */
295 uint csc_yof; /* _WINC_CSC_YOF_0 */
296 uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */
297 uint csc_kur; /* _WINC_CSC_KUR_0 */
298 uint csc_kvr; /* _WINC_CSC_KVR_0 */
299 uint csc_kug; /* _WINC_CSC_KUG_0 */
300 uint csc_kvg; /* _WINC_CSC_KVG_0 */
301 uint csc_kub; /* _WINC_CSC_KUB_0 */
302 uint csc_kvb; /* _WINC_CSC_KVB_0 */
304 /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
305 uint v_filter_p[WINC_FILTER_COUNT];
308 /* WIN A/B/C Register 0x700 ~ 0x714*/
310 /* Address 0x700 ~ 0x714 */
311 uint win_opt; /* _WIN_WIN_OPTIONS_0 */
312 uint byte_swap; /* _WIN_BYTE_SWAP_0 */
313 uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */
314 uint color_depth; /* _WIN_COLOR_DEPTH_0 */
315 uint pos; /* _WIN_POSITION_0 */
316 uint size; /* _WIN_SIZE_0 */
317 uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */
318 uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */
319 uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */
320 uint dda_increment; /* _WIN_DDA_INCREMENT_0 */
321 uint line_stride; /* _WIN_LINE_STRIDE_0 */
322 uint buf_stride; /* _WIN_BUF_STRIDE_0 */
323 uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */
324 uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */
325 uint dv_ctrl; /* _WIN_DV_CONTROL_0 */
326 uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */
327 uint blend_1win; /* _WIN_BLEND_1WIN_0 */
328 uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */
329 uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */
330 uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */
331 uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */
334 /* WINBUF A/B/C Register 0x800 ~ 0x80a */
335 struct dc_winbuf_reg {
336 /* Address 0x800 ~ 0x80a */
337 uint start_addr; /* _WINBUF_START_ADDR_0 */
338 uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */
339 uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */
340 uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */
341 uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */
342 uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */
343 uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */
344 uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */
345 uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */
346 uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */
347 uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */
350 /* Display Controller (DC_) regs */
352 struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */
353 uint reserved0[0x2bc];
355 struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */
356 uint reserved1[0xd6];
358 struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4c1 */
359 uint reserved2[0x3e];
361 struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */
362 uint reserved3[0xd7];
364 struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x714*/
365 uint reserved4[0xeb];
367 struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80a */
370 #define BIT(pos) (1U << pos)
372 /* DC_CMD_DISPLAY_COMMAND 0x032 */
373 #define CTRL_MODE_SHIFT 5
374 #define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
378 CTRL_MODE_NC_DISPLAY,
381 /* _WIN_COLOR_DEPTH_0 */
382 enum win_color_depth_id {
387 COLOR_DEPTH_B4G4R4A4,
391 COLOR_DEPTH_B8G8R8A8 = 12,
392 COLOR_DEPTH_R8G8B8A8,
393 COLOR_DEPTH_B6x2G6x2R6x2A8,
394 COLOR_DEPTH_R6x2G6x2B6x2A8,
395 COLOR_DEPTH_YCbCr422,
397 COLOR_DEPTH_YCbCr420P,
399 COLOR_DEPTH_YCbCr422P,
401 COLOR_DEPTH_YCbCr422R,
403 COLOR_DEPTH_YCbCr422RA,
404 COLOR_DEPTH_YUV422RA,
407 /* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
408 #define PW0_ENABLE BIT(0)
409 #define PW1_ENABLE BIT(2)
410 #define PW2_ENABLE BIT(4)
411 #define PW3_ENABLE BIT(6)
412 #define PW4_ENABLE BIT(8)
413 #define PM0_ENABLE BIT(16)
414 #define PM1_ENABLE BIT(18)
415 #define SPI_ENABLE BIT(24)
416 #define HSPI_ENABLE BIT(25)
418 /* DC_CMD_STATE_CONTROL 0x041 */
419 #define GENERAL_ACT_REQ BIT(0)
420 #define WIN_A_ACT_REQ BIT(1)
421 #define WIN_B_ACT_REQ BIT(2)
422 #define WIN_C_ACT_REQ BIT(3)
423 #define GENERAL_UPDATE BIT(8)
424 #define WIN_A_UPDATE BIT(9)
425 #define WIN_B_UPDATE BIT(10)
426 #define WIN_C_UPDATE BIT(11)
428 /* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
429 #define WINDOW_A_SELECT BIT(4)
430 #define WINDOW_B_SELECT BIT(5)
431 #define WINDOW_C_SELECT BIT(6)
433 /* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
434 #define SHIFT_CLK_DIVIDER_SHIFT 0
435 #define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT)
436 #define PIXEL_CLK_DIVIDER_SHIFT 8
437 #define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT)
439 PIXEL_CLK_DIVIDER_PCD1,
440 PIXEL_CLK_DIVIDER_PCD1H,
441 PIXEL_CLK_DIVIDER_PCD2,
442 PIXEL_CLK_DIVIDER_PCD3,
443 PIXEL_CLK_DIVIDER_PCD4,
444 PIXEL_CLK_DIVIDER_PCD6,
445 PIXEL_CLK_DIVIDER_PCD8,
446 PIXEL_CLK_DIVIDER_PCD9,
447 PIXEL_CLK_DIVIDER_PCD12,
448 PIXEL_CLK_DIVIDER_PCD16,
449 PIXEL_CLK_DIVIDER_PCD18,
450 PIXEL_CLK_DIVIDER_PCD24,
451 PIXEL_CLK_DIVIDER_PCD13,
454 /* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
455 #define DATA_FORMAT_SHIFT 0
456 #define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT)
459 DATA_FORMAT_DF1P2C24B,
460 DATA_FORMAT_DF1P2C18B,
461 DATA_FORMAT_DF1P2C16B,
465 DATA_FORMAT_DF1P3C24B,
466 DATA_FORMAT_DF1P3C18B,
468 #define DATA_ALIGNMENT_SHIFT 8
473 #define DATA_ORDER_SHIFT 9
479 /* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
480 #define DE_SELECT_SHIFT 0
481 #define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
482 #define DE_SELECT_ACTIVE_BLANK 0x0
483 #define DE_SELECT_ACTIVE 0x1
484 #define DE_SELECT_ACTIVE_IS 0x2
485 #define DE_CONTROL_SHIFT 2
486 #define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT)
490 DE_CONTROL_EARLY_EXT,
492 DE_CONTROL_ACTIVE_BLANK,
495 /* DC_WIN_WIN_OPTIONS 0x700 */
496 #define H_DIRECTION BIT(0)
498 H_DIRECTION_INCREMENT,
499 H_DIRECTION_DECREMENT,
501 #define V_DIRECTION BIT(2)
503 V_DIRECTION_INCREMENT,
504 V_DIRECTION_DECREMENT,
506 #define COLOR_EXPAND BIT(6)
507 #define CP_ENABLE BIT(16)
508 #define DV_ENABLE BIT(20)
509 #define WIN_ENABLE BIT(30)
511 /* DC_WIN_BYTE_SWAP 0x701 */
512 #define BYTE_SWAP_SHIFT 0
513 #define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT)
521 /* DC_WIN_POSITION 0x704 */
522 #define H_POSITION_SHIFT 0
523 #define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT)
524 #define V_POSITION_SHIFT 16
525 #define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT)
527 /* DC_WIN_SIZE 0x705 */
528 #define H_SIZE_SHIFT 0
529 #define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT)
530 #define V_SIZE_SHIFT 16
531 #define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT)
533 /* DC_WIN_PRESCALED_SIZE 0x706 */
534 #define H_PRESCALED_SIZE_SHIFT 0
535 #define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE)
536 #define V_PRESCALED_SIZE_SHIFT 16
537 #define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE)
539 /* DC_WIN_DDA_INCREMENT 0x709 */
540 #define H_DDA_INC_SHIFT 0
541 #define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT)
542 #define V_DDA_INC_SHIFT 16
543 #define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
545 #endif /* __ASM_ARCH_TEGRA_DC_H */