2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra20 clock PLL tables */
10 #ifndef _CLOCK_TABLES_H_
11 #define _CLOCK_TABLES_H_
13 /* The PLLs supported by the hardware */
16 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
23 /* now the simple ones */
24 CLOCK_ID_FIRST_SIMPLE,
25 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
29 /* These are the base clocks (inputs to the Tegra SOC) */
33 CLOCK_ID_COUNT, /* number of clocks */
37 /* The clocks supported by the hardware */
42 PERIPH_ID_CPU = PERIPH_ID_FIRST,
81 /* Middle word: 63:32 */
112 PERIPH_ID_RESERVED56,
121 /* Upper word 95:64 */
136 PERIPH_ID_RESERVED76,
137 PERIPH_ID_RESERVED77,
138 PERIPH_ID_RESERVED78,
139 PERIPH_ID_RESERVED79,
142 PERIPH_ID_RESERVED80,
143 PERIPH_ID_RESERVED81,
144 PERIPH_ID_RESERVED82,
145 PERIPH_ID_RESERVED83,
153 PERIPH_ID_SYNC_CLK_DOUBLER,
154 PERIPH_ID_CLK_M_DOUBLER,
155 PERIPH_ID_RESERVED91,
171 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
172 #define PERIPH_REG(id) ((id) >> 5)
174 /* Mask value for a clock (within PERIPH_REG(id)) */
175 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
177 /* return 1 if a PLL ID is in range, and not a simple PLL */
178 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
179 (id) < CLOCK_ID_FIRST_SIMPLE)
181 /* return 1 if a peripheral ID is in range */
182 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
183 (id) < PERIPH_ID_COUNT)
185 #endif /* _CLOCK_TABLES_H_ */