2 * (C) Copyright 2010-2014
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA_PINMUX_H_
9 #define _TEGRA_PINMUX_H_
11 #include <asm/arch/tegra.h>
13 /* The pullup/pulldown state of a pin group */
20 /* Defines whether a pin group is tristated or in normal operation */
23 PMUX_TRI_TRISTATE = 1,
26 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
34 PMUX_PIN_LOCK_DEFAULT = 0,
35 PMUX_PIN_LOCK_DISABLE,
40 PMUX_PIN_OD_DEFAULT = 0,
45 enum pmux_pin_ioreset {
46 PMUX_PIN_IO_RESET_DEFAULT = 0,
47 PMUX_PIN_IO_RESET_DISABLE,
48 PMUX_PIN_IO_RESET_ENABLE,
51 #ifdef TEGRA_PMX_HAS_RCV_SEL
52 enum pmux_pin_rcv_sel {
53 PMUX_PIN_RCV_SEL_DEFAULT = 0,
54 PMUX_PIN_RCV_SEL_NORMAL,
55 PMUX_PIN_RCV_SEL_HIGH,
57 #endif /* TEGRA_PMX_HAS_RCV_SEL */
58 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
61 * This defines the configuration for a pin, including the function assigned,
62 * pull up/down settings and tristate settings. Having set up one of these
63 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
64 * available is pinmux_config_table() to configure a list of pins.
66 struct pmux_pingrp_config {
67 enum pmux_pingrp pingrp; /* pin group PMUX_PINGRP_... */
68 enum pmux_func func; /* function to assign PMUX_FUNC_... */
69 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
70 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
71 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
72 enum pmux_pin_io io; /* input or output PMUX_PIN_... */
73 enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
74 enum pmux_pin_od od; /* open-drain or push-pull driver */
75 enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
76 #ifdef TEGRA_PMX_HAS_RCV_SEL
77 enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
78 /* VIL/VIH receivers */
83 /* Set the mux function for a pin group */
84 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
86 /* Set the pull up/down feature for a pin group */
87 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
89 /* Set a pin group to tristate */
90 void pinmux_tristate_enable(enum pmux_pingrp pin);
92 /* Set a pin group to normal (non tristate) */
93 void pinmux_tristate_disable(enum pmux_pingrp pin);
95 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
96 /* Set a pin group as input or output */
97 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
101 * Configure a list of pin groups
103 * @param config List of config items
104 * @param len Number of config items in list
106 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
109 #ifdef TEGRA_PMX_HAS_DRVGRPS
111 #define PMUX_SLWF_MIN 0
112 #define PMUX_SLWF_MAX 3
113 #define PMUX_SLWF_NONE -1
115 #define PMUX_SLWR_MIN 0
116 #define PMUX_SLWR_MAX 3
117 #define PMUX_SLWR_NONE -1
119 #define PMUX_DRVUP_MIN 0
120 #define PMUX_DRVUP_MAX 127
121 #define PMUX_DRVUP_NONE -1
123 #define PMUX_DRVDN_MIN 0
124 #define PMUX_DRVDN_MAX 127
125 #define PMUX_DRVDN_NONE -1
127 /* Defines a pin group cfg's low-power mode select */
136 /* Defines whether a pin group cfg's schmidt is enabled or not */
138 PMUX_SCHMT_DISABLE = 0,
139 PMUX_SCHMT_ENABLE = 1,
140 PMUX_SCHMT_NONE = -1,
143 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
145 PMUX_HSM_DISABLE = 0,
151 * This defines the configuration for a pin group's pad control config
153 struct pmux_drvgrp_config {
154 enum pmux_drvgrp drvgrp; /* pin group PMUX_DRVGRP_x */
155 int slwf; /* falling edge slew */
156 int slwr; /* rising edge slew */
157 int drvup; /* pull-up drive strength */
158 int drvdn; /* pull-down drive strength */
159 enum pmux_lpmd lpmd; /* low-power mode selection */
160 enum pmux_schmt schmt; /* schmidt enable */
161 enum pmux_hsm hsm; /* high-speed mode enable */
165 * Set the GP pad configs
167 * @param config List of config items
168 * @param len Number of config items in list
170 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
173 #endif /* TEGRA_PMX_HAS_DRVGRPS */
175 struct pmux_pingrp_desc {
176 enum pmux_func funcs[4];
177 #if defined(CONFIG_TEGRA20)
180 #endif /* CONFIG_TEGRA20 */
183 extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
185 #endif /* _TEGRA_PINMUX_H_ */