2 * (C) Copyright 2010-2014
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA_PINMUX_H_
9 #define _TEGRA_PINMUX_H_
11 #include <linux/types.h>
13 #include <asm/arch/tegra.h>
15 /* The pullup/pulldown state of a pin group */
22 /* Defines whether a pin group is tristated or in normal operation */
25 PMUX_TRI_TRISTATE = 1,
28 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
36 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
38 PMUX_PIN_LOCK_DEFAULT = 0,
39 PMUX_PIN_LOCK_DISABLE,
44 #ifdef TEGRA_PMX_PINS_HAVE_OD
46 PMUX_PIN_OD_DEFAULT = 0,
52 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
53 enum pmux_pin_ioreset {
54 PMUX_PIN_IO_RESET_DEFAULT = 0,
55 PMUX_PIN_IO_RESET_DISABLE,
56 PMUX_PIN_IO_RESET_ENABLE,
60 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
61 enum pmux_pin_rcv_sel {
62 PMUX_PIN_RCV_SEL_DEFAULT = 0,
63 PMUX_PIN_RCV_SEL_NORMAL,
64 PMUX_PIN_RCV_SEL_HIGH,
68 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
69 enum pmux_pin_e_io_hv {
70 PMUX_PIN_E_IO_HV_DEFAULT = 0,
71 PMUX_PIN_E_IO_HV_NORMAL,
72 PMUX_PIN_E_IO_HV_HIGH,
76 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
77 /* Defines a pin group cfg's low-power mode select */
87 #if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
88 /* Defines whether a pin group cfg's schmidt is enabled or not */
90 PMUX_SCHMT_DISABLE = 0,
91 PMUX_SCHMT_ENABLE = 1,
96 #if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
97 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
106 * This defines the configuration for a pin, including the function assigned,
107 * pull up/down settings and tristate settings. Having set up one of these
108 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
109 * available is pinmux_config_table() to configure a list of pins.
111 struct pmux_pingrp_config {
112 u32 pingrp:16; /* pin group PMUX_PINGRP_... */
113 u32 func:8; /* function to assign PMUX_FUNC_... */
114 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
115 u32 tristate:2; /* tristate or normal PMUX_TRI_... */
116 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
117 u32 io:2; /* input or output PMUX_PIN_... */
119 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
120 u32 lock:2; /* lock enable/disable PMUX_PIN... */
122 #ifdef TEGRA_PMX_PINS_HAVE_OD
123 u32 od:2; /* open-drain or push-pull driver */
125 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
126 u32 ioreset:2; /* input/output reset PMUX_PIN... */
128 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
129 u32 rcv_sel:2; /* select between High and Normal */
130 /* VIL/VIH receivers */
132 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
133 u32 e_io_hv:2; /* select 3.3v tolerant receivers */
135 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
136 u32 schmt:2; /* schmitt enable */
138 #ifdef TEGRA_PMX_PINS_HAVE_HSM
139 u32 hsm:2; /* high-speed mode enable */
143 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
144 /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
145 void pinmux_set_tristate_input_clamping(void);
146 void pinmux_clear_tristate_input_clamping(void);
149 /* Set the mux function for a pin group */
150 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
152 /* Set the pull up/down feature for a pin group */
153 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
155 /* Set a pin group to tristate */
156 void pinmux_tristate_enable(enum pmux_pingrp pin);
158 /* Set a pin group to normal (non tristate) */
159 void pinmux_tristate_disable(enum pmux_pingrp pin);
161 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
162 /* Set a pin group as input or output */
163 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
167 * Configure a list of pin groups
169 * @param config List of config items
170 * @param len Number of config items in list
172 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
175 struct pmux_pingrp_desc {
177 #if defined(CONFIG_TEGRA20)
180 #endif /* CONFIG_TEGRA20 */
183 extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
185 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
187 #define PMUX_SLWF_MIN 0
188 #define PMUX_SLWF_MAX 3
189 #define PMUX_SLWF_NONE -1
191 #define PMUX_SLWR_MIN 0
192 #define PMUX_SLWR_MAX 3
193 #define PMUX_SLWR_NONE -1
195 #define PMUX_DRVUP_MIN 0
196 #define PMUX_DRVUP_MAX 127
197 #define PMUX_DRVUP_NONE -1
199 #define PMUX_DRVDN_MIN 0
200 #define PMUX_DRVDN_MAX 127
201 #define PMUX_DRVDN_NONE -1
204 * This defines the configuration for a pin group's pad control config
206 struct pmux_drvgrp_config {
207 u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */
208 u32 slwf:3; /* falling edge slew */
209 u32 slwr:3; /* rising edge slew */
210 u32 drvup:8; /* pull-up drive strength */
211 u32 drvdn:8; /* pull-down drive strength */
212 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
213 u32 lpmd:3; /* low-power mode selection */
215 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
216 u32 schmt:2; /* schmidt enable */
218 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
219 u32 hsm:2; /* high-speed mode enable */
224 * Set the GP pad configs
226 * @param config List of config items
227 * @param len Number of config items in list
229 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
232 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
234 #ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
235 struct pmux_mipipadctrlgrp_config {
236 u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */
237 u32 func:8; /* function to assign PMUX_FUNC_... */
240 void pinmux_config_mipipadctrlgrp_table(
241 const struct pmux_mipipadctrlgrp_config *config, int len);
243 struct pmux_mipipadctrlgrp_desc {
247 extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
248 #endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
250 #endif /* _TEGRA_PINMUX_H_ */