2 * Sun8i platform dram controller register and constant defines
4 * (C) Copyright 2007-2015 Allwinner Technology Co.
5 * Jerry Wang <wangflord@allwinnertech.com>
6 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
7 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 #ifndef _SUNXI_DRAM_SUN8I_A83T_H
13 #define _SUNXI_DRAM_SUN8I_A83T_H
15 struct sunxi_mctl_com_reg {
17 u32 ccr; /* 0x04 controller configuration register */
19 u8 res0[0x4]; /* 0x0c */
20 u32 mcr0_0; /* 0x10 */
21 u32 mcr1_0; /* 0x14 */
22 u32 mcr0_1; /* 0x18 */
23 u32 mcr1_1; /* 0x1c */
24 u32 mcr0_2; /* 0x20 */
25 u32 mcr1_2; /* 0x24 */
26 u32 mcr0_3; /* 0x28 */
27 u32 mcr1_3; /* 0x2c */
28 u32 mcr0_4; /* 0x30 */
29 u32 mcr1_4; /* 0x34 */
30 u32 mcr0_5; /* 0x38 */
31 u32 mcr1_5; /* 0x3c */
32 u32 mcr0_6; /* 0x40 */
33 u32 mcr1_6; /* 0x44 */
34 u32 mcr0_7; /* 0x48 */
35 u32 mcr1_7; /* 0x4c */
36 u32 mcr0_8; /* 0x50 */
37 u32 mcr1_8; /* 0x54 */
38 u32 mcr0_9; /* 0x58 */
39 u32 mcr1_9; /* 0x5c */
40 u32 mcr0_10; /* 0x60 */
41 u32 mcr1_10; /* 0x64 */
42 u32 mcr0_11; /* 0x68 */
43 u32 mcr1_11; /* 0x6c */
44 u32 mcr0_12; /* 0x70 */
45 u32 mcr1_12; /* 0x74 */
46 u32 mcr0_13; /* 0x78 */
47 u32 mcr1_13; /* 0x7c */
48 u32 mcr0_14; /* 0x80 */
49 u32 mcr1_14; /* 0x84 */
50 u32 mcr0_15; /* 0x88 */
51 u32 mcr1_15; /* 0x8c */
57 u8 res2[0x8]; /* 0xa4 */
58 u32 swoffr; /* 0xac */
59 u8 res3[0x10]; /* 0xb0 */
61 u8 res4[0x3c]; /* 0xc4 */
62 u32 mdfscr; /* 0x100 */
63 u32 mdfsmer; /* 0x104 */
66 struct sunxi_mctl_ctl_reg {
68 u32 pwrctl; /* 0x04 */
69 u32 mrctrl0; /* 0x08 */
74 u8 res1[0x14]; /* 0x1c */
79 u32 pllgcr; /* 0x40 */
85 u32 dramtmg0; /* 0x58 dram timing parameters register 0 */
86 u32 dramtmg1; /* 0x5c dram timing parameters register 1 */
87 u32 dramtmg2; /* 0x60 dram timing parameters register 2 */
88 u32 dramtmg3; /* 0x64 dram timing parameters register 3 */
89 u32 dramtmg4; /* 0x68 dram timing parameters register 4 */
90 u32 dramtmg5; /* 0x6c dram timing parameters register 5 */
91 u32 dramtmg6; /* 0x70 dram timing parameters register 6 */
92 u32 dramtmg7; /* 0x74 dram timing parameters register 7 */
93 u32 dramtmg8; /* 0x78 dram timing parameters register 8 */
94 u32 odtcfg; /* 0x7c */
95 u32 pitmg0; /* 0x80 */
96 u32 pitmg1; /* 0x84 */
97 u8 res2[0x4]; /* 0x88 */
98 u32 rfshctl0; /* 0x8c */
99 u32 rfshtmg; /* 0x90 */
100 u32 rfshctl1; /* 0x94 */
101 u32 pwrtmg; /* 0x98 */
102 u8 res3[0x20]; /* 0x9c */
103 u32 dqsgmr; /* 0xbc */
105 u32 dtar0; /* 0xc4 */
106 u32 dtar1; /* 0xc8 */
107 u32 dtar2; /* 0xcc */
108 u32 dtar3; /* 0xd0 */
109 u32 dtdr0; /* 0xd4 */
110 u32 dtdr1; /* 0xd8 */
111 u32 dtmr0; /* 0xdc */
112 u32 dtmr1; /* 0xe0 */
113 u32 dtbmr; /* 0xe4 */
114 u32 catr0; /* 0xe8 */
115 u32 catr1; /* 0xec */
116 u32 dtedr0; /* 0xf0 */
117 u32 dtedr1; /* 0xf4 */
118 u8 res4[0x8]; /* 0xf8 */
119 u32 pgcr0; /* 0x100 */
120 u32 pgcr1; /* 0x104 */
121 u32 pgcr2; /* 0x108 */
122 u32 pgcr3; /* 0x10c */
123 u32 iovcr0; /* 0x110 */
124 u32 iovcr1; /* 0x114 */
125 u32 dqsdr; /* 0x118 */
126 u32 dxccr; /* 0x11c */
127 u32 odtmap; /* 0x120 */
128 u32 zqctl0; /* 0x124 */
129 u32 zqctl1; /* 0x128 */
130 u8 res6[0x14]; /* 0x12c */
131 u32 zqncr; /* 0x140 zq control register 0 */
132 u32 zqnpr; /* 0x144 zq control register 1 */
133 u32 zqndr; /* 0x148 zq control register 2 */
134 u32 zqnsr; /* 0x14c zq status register 0 */
135 u32 res7; /* 0x150 zq status register 1 */
136 u8 res8[0x6c]; /* 0x154 */
137 u32 sched; /* 0x1c0 */
138 u32 perfhpr0; /* 0x1c4 */
139 u32 perfhpr1; /* 0x1c8 */
140 u32 perflpr0; /* 0x1cc */
141 u32 perflpr1; /* 0x1d0 */
142 u32 perfwr0; /* 0x1d4 */
143 u32 perfwr1; /* 0x1d8 */
147 #define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
148 #define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
149 #define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)
151 #define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
152 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
153 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
154 #define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
155 #define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
157 #define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x))
158 #define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x)
159 #define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300)
160 #define DXnLCDLR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x)
161 #define DXnLCDLR1(x) (SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x)
162 #define DXnLCDLR2(x) (SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x)
163 #define DATX0IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x)
164 #define DATX1IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x)
165 #define DATX2IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x)
166 #define DATX3IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x)
167 #define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880)
168 #define MX_UPD2 (SUNXI_DRAM_CTL0_BASE + 0x00000888)
170 #define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800)
171 #define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x)
172 #define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x)
175 * DRAM common (sunxi_mctl_com_reg) register constants.
177 #define MCTL_CR_RANK_MASK (3 << 0)
178 #define MCTL_CR_RANK(x) (((x) - 1) << 0)
179 #define MCTL_CR_BANK_MASK (3 << 2)
180 #define MCTL_CR_BANK(x) ((x) << 2)
181 #define MCTL_CR_ROW_MASK (0xf << 4)
182 #define MCTL_CR_ROW(x) (((x) - 1) << 4)
183 #define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
184 #define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
185 #define MCTL_CR_BUSW_MASK (7 << 12)
186 #define MCTL_CR_BUSW8 (0 << 12)
187 #define MCTL_CR_BUSW16 (1 << 12)
188 #define MCTL_CR_SEQUENCE (1 << 15)
189 #define MCTL_CR_DRAM_TYPE(x) ((x) << 16)
190 #define MCTL_CR_CHANNEL_MASK (1 << 19)
191 #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19)
192 #define MCTL_CR_UNKNOWN (0x4 << 20)
193 #define MCTL_CR_CS1_CONTROL(x) ((x) << 24)
195 /* DRAM control (sunxi_mctl_ctl_reg) register constants */
196 #define MCTL_MR0 0x1c70 /* CL=11, WR=12 */
197 #define MCTL_MR1 0x40
198 #define MCTL_MR2 0x18 /* CWL=8 */
201 #define MCTL_LPDDR3_MR0 0x0
202 #define MCTL_LPDDR3_MR1 0xc3 /* twr=8, bl=8 */
203 #define MCTL_LPDDR3_MR2 0xa /* RL=12, CWL=6 */
204 #define MCTL_LPDDR3_MR3 0x0
206 #define DRAM_TYPE_DDR3 3
207 #define DRAM_TYPE_LPDDR3 7
208 #endif /* _SUNXI_DRAM_SUN8I_A83T_H */