arch/arm/include/asm/arch-sunxi/display.h

   1 /*
   2  * Sunxi platform display controller register and constant defines
   3  *
   4  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _SUNXI_DISPLAY_H
  10 #define _SUNXI_DISPLAY_H
  11
  12 struct sunxi_de_be_reg {
  13         u8 res0[0x800];                 /* 0x000 */
  14         u32 mode;                       /* 0x800 */
  15         u32 backcolor;                  /* 0x804 */
  16         u32 disp_size;                  /* 0x808 */
  17         u8 res1[0x4];                   /* 0x80c */
  18         u32 layer0_size;                /* 0x810 */
  19         u32 layer1_size;                /* 0x814 */
  20         u32 layer2_size;                /* 0x818 */
  21         u32 layer3_size;                /* 0x81c */
  22         u32 layer0_pos;                 /* 0x820 */
  23         u32 layer1_pos;                 /* 0x824 */
  24         u32 layer2_pos;                 /* 0x828 */
  25         u32 layer3_pos;                 /* 0x82c */
  26         u8 res2[0x10];                  /* 0x830 */
  27         u32 layer0_stride;              /* 0x840 */
  28         u32 layer1_stride;              /* 0x844 */
  29         u32 layer2_stride;              /* 0x848 */
  30         u32 layer3_stride;              /* 0x84c */
  31         u32 layer0_addr_low32b;         /* 0x850 */
  32         u32 layer1_addr_low32b;         /* 0x854 */
  33         u32 layer2_addr_low32b;         /* 0x858 */
  34         u32 layer3_addr_low32b;         /* 0x85c */
  35         u32 layer0_addr_high4b;         /* 0x860 */
  36         u32 layer1_addr_high4b;         /* 0x864 */
  37         u32 layer2_addr_high4b;         /* 0x868 */
  38         u32 layer3_addr_high4b;         /* 0x86c */
  39         u32 reg_ctrl;                   /* 0x870 */
  40         u8 res3[0xc];                   /* 0x874 */
  41         u32 color_key_max;              /* 0x880 */
  42         u32 color_key_min;              /* 0x884 */
  43         u32 color_key_config;           /* 0x888 */
  44         u8 res4[0x4];                   /* 0x88c */
  45         u32 layer0_attr0_ctrl;          /* 0x890 */
  46         u32 layer1_attr0_ctrl;          /* 0x894 */
  47         u32 layer2_attr0_ctrl;          /* 0x898 */
  48         u32 layer3_attr0_ctrl;          /* 0x89c */
  49         u32 layer0_attr1_ctrl;          /* 0x8a0 */
  50         u32 layer1_attr1_ctrl;          /* 0x8a4 */
  51         u32 layer2_attr1_ctrl;          /* 0x8a8 */
  52         u32 layer3_attr1_ctrl;          /* 0x8ac */
  53 };
  54
  55 struct sunxi_lcdc_reg {
  56         u32 ctrl;                       /* 0x00 */
  57         u32 int0;                       /* 0x04 */
  58         u32 int1;                       /* 0x08 */
  59         u8 res0[0x04];                  /* 0x0c */
  60         u32 frame_ctrl;                 /* 0x10 */
  61         u8 res1[0x2c];                  /* 0x14 */
  62         u32 tcon0_ctrl;                 /* 0x40 */
  63         u32 tcon0_dclk;                 /* 0x44 */
  64         u32 tcon0_basic_timing0;        /* 0x48 */
  65         u32 tcon0_basic_timing1;        /* 0x4c */
  66         u32 tcon0_basic_timing2;        /* 0x50 */
  67         u32 tcon0_basic_timing3;        /* 0x54 */
  68         u32 tcon0_hv_intf;              /* 0x58 */
  69         u8 res2[0x04];                  /* 0x5c */
  70         u32 tcon0_cpu_intf;             /* 0x60 */
  71         u32 tcon0_cpu_wr_dat;           /* 0x64 */
  72         u32 tcon0_cpu_rd_dat0;          /* 0x68 */
  73         u32 tcon0_cpu_rd_dat1;          /* 0x6c */
  74         u32 tcon0_ttl_timing0;          /* 0x70 */
  75         u32 tcon0_ttl_timing1;          /* 0x74 */
  76         u32 tcon0_ttl_timing2;          /* 0x78 */
  77         u32 tcon0_ttl_timing3;          /* 0x7c */
  78         u32 tcon0_ttl_timing4;          /* 0x80 */
  79         u32 tcon0_lvds_intf;            /* 0x84 */
  80         u32 tcon0_io_polarity;          /* 0x88 */
  81         u32 tcon0_io_tristate;          /* 0x8c */
  82         u32 tcon1_ctrl;                 /* 0x90 */
  83         u32 tcon1_timing_source;        /* 0x94 */
  84         u32 tcon1_timing_scale;         /* 0x98 */
  85         u32 tcon1_timing_out;           /* 0x9c */
  86         u32 tcon1_timing_h;             /* 0xa0 */
  87         u32 tcon1_timing_v;             /* 0xa4 */
  88         u32 tcon1_timing_sync;          /* 0xa8 */
  89         u8 res3[0x44];                  /* 0xac */
  90         u32 tcon1_io_polarity;          /* 0xf0 */
  91         u32 tcon1_io_tristate;          /* 0xf4 */
  92 };
  93
  94 struct sunxi_hdmi_reg {
  95         u32 version_id;                 /* 0x000 */
  96         u32 ctrl;                       /* 0x004 */
  97         u32 irq;                        /* 0x008 */
  98         u32 hpd;                        /* 0x00c */
  99         u32 video_ctrl;                 /* 0x010 */
 100         u32 video_size;                 /* 0x014 */
 101         u32 video_bp;                   /* 0x018 */
 102         u32 video_fp;                   /* 0x01c */
 103         u32 video_spw;                  /* 0x020 */
 104         u32 video_polarity;             /* 0x024 */
 105         u8 res0[0x58];                  /* 0x028 */
 106         u8 avi_info_frame[0x14];        /* 0x080 */
 107         u8 res1[0x4c];                  /* 0x094 */
 108         u32 qcp_packet0;                /* 0x0e0 */
 109         u32 qcp_packet1;                /* 0x0e4 */
 110         u8 res2[0x118];                 /* 0x0e8 */
 111         u32 pad_ctrl0;                  /* 0x200 */
 112         u32 pad_ctrl1;                  /* 0x204 */
 113         u32 pll_ctrl;                   /* 0x208 */
 114         u32 pll_dbg0;                   /* 0x20c */
 115         u32 pll_dbg1;                   /* 0x210 */
 116         u32 hpd_cec;                    /* 0x214 */
 117         u8 res3[0x28];                  /* 0x218 */
 118         u8 vendor_info_frame[0x14];     /* 0x240 */
 119         u8 res4[0x9c];                  /* 0x254 */
 120         u32 pkt_ctrl0;                  /* 0x2f0 */
 121         u32 pkt_ctrl1;                  /* 0x2f4 */
 122         u8 res5[0x8];                   /* 0x2f8 */
 123         u32 unknown;                    /* 0x300 */
 124         u8 res6[0xc];                   /* 0x304 */
 125         u32 audio_sample_count;         /* 0x310 */
 126         u8 res7[0xec];                  /* 0x314 */
 127         u32 audio_tx_fifo;              /* 0x400 */
 128         u8 res8[0xfc];                  /* 0x404 */
 129 #ifndef CONFIG_MACH_SUN6I
 130         u32 ddc_ctrl;                   /* 0x500 */
 131         u32 ddc_addr;                   /* 0x504 */
 132         u32 ddc_int_mask;               /* 0x508 */
 133         u32 ddc_int_status;             /* 0x50c */
 134         u32 ddc_fifo_ctrl;              /* 0x510 */
 135         u32 ddc_fifo_status;            /* 0x514 */
 136         u32 ddc_fifo_data;              /* 0x518 */
 137         u32 ddc_byte_count;             /* 0x51c */
 138         u32 ddc_cmnd;                   /* 0x520 */
 139         u32 ddc_exreg;                  /* 0x524 */
 140         u32 ddc_clock;                  /* 0x528 */
 141         u8 res9[0x14];                  /* 0x52c */
 142         u32 ddc_line_ctrl;              /* 0x540 */
 143 #else
 144         u32 ddc_ctrl;                   /* 0x500 */
 145         u32 ddc_exreg;                  /* 0x504 */
 146         u32 ddc_cmnd;                   /* 0x508 */
 147         u32 ddc_addr;                   /* 0x50c */
 148         u32 ddc_int_mask;               /* 0x510 */
 149         u32 ddc_int_status;             /* 0x514 */
 150         u32 ddc_fifo_ctrl;              /* 0x518 */
 151         u32 ddc_fifo_status;            /* 0x51c */
 152         u32 ddc_clock;                  /* 0x520 */
 153         u32 ddc_timeout;                /* 0x524 */
 154         u8 res9[0x18];                  /* 0x528 */
 155         u32 ddc_dbg;                    /* 0x540 */
 156         u8 res10[0x3c];                 /* 0x544 */
 157         u32 ddc_fifo_data;              /* 0x580 */
 158 #endif
 159 };
 160
 161 /*
 162  * DE-BE register constants.
 163  */
 164 #define SUNXI_DE_BE_WIDTH(x)                    (((x) - 1) << 0)
 165 #define SUNXI_DE_BE_HEIGHT(y)                   (((y) - 1) << 16)
 166 #define SUNXI_DE_BE_MODE_ENABLE                 (1 << 0)
 167 #define SUNXI_DE_BE_MODE_START                  (1 << 1)
 168 #define SUNXI_DE_BE_MODE_LAYER0_ENABLE          (1 << 8)
 169 #define SUNXI_DE_BE_LAYER_STRIDE(x)             ((x) << 5)
 170 #define SUNXI_DE_BE_REG_CTRL_LOAD_REGS          (1 << 0)
 171 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888    (0x09 << 8)
 172
 173 /*
 174  * LCDC register constants.
 175  */
 176 #define SUNXI_LCDC_X(x)                         (((x) - 1) << 16)
 177 #define SUNXI_LCDC_Y(y)                         (((y) - 1) << 0)
 178 #define SUNXI_LCDC_CTRL_IO_MAP_MASK             (1 << 0)
 179 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0            (0 << 0)
 180 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1            (1 << 0)
 181 #define SUNXI_LCDC_CTRL_TCON_ENABLE             (1 << 31)
 182 #define SUNXI_LCDC_TCON0_DCLK_ENABLE            (0xf << 28)
 183 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)      (((n) & 0x1f) << 4)
 184 #define SUNXI_LCDC_TCON1_CTRL_ENABLE            (1 << 31)
 185 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n)         (((n) - 1) << 0)
 186 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)      (((n) - 1) << 16)
 187 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n)         (((n) - 1) << 0)
 188 #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)      (((n) * 2) << 16)
 189
 190 /*
 191  * HDMI register constants.
 192  */
 193 #define SUNXI_HDMI_X(x)                         (((x) - 1) << 0)
 194 #define SUNXI_HDMI_Y(y)                         (((y) - 1) << 16)
 195 #define SUNXI_HDMI_CTRL_ENABLE                  (1 << 31)
 196 #define SUNXI_HDMI_IRQ_STATUS_FIFO_UF           (1 << 0)
 197 #define SUNXI_HDMI_IRQ_STATUS_FIFO_OF           (1 << 1)
 198 #define SUNXI_HDMI_IRQ_STATUS_BITS              0x73
 199 #define SUNXI_HDMI_HPD_DETECT                   (1 << 0)
 200 #define SUNXI_HDMI_VIDEO_CTRL_ENABLE            (1 << 31)
 201 #define SUNXI_HDMI_VIDEO_CTRL_HDMI              (1 << 30)
 202 #define SUNXI_HDMI_VIDEO_POL_HOR                (1 << 0)
 203 #define SUNXI_HDMI_VIDEO_POL_VER                (1 << 1)
 204 #define SUNXI_HDMI_VIDEO_POL_TX_CLK             (0x3e0 << 16)
 205 #define SUNXI_HDMI_QCP_PACKET0                  3
 206 #define SUNXI_HDMI_QCP_PACKET1                  0
 207
 208 #ifdef CONFIG_MACH_SUN6I
 209 #define SUNXI_HDMI_PAD_CTRL0_HDP                0x7e80000f
 210 #define SUNXI_HDMI_PAD_CTRL0_RUN                0x7e8000ff
 211 #else
 212 #define SUNXI_HDMI_PAD_CTRL0_HDP                0xfe800000
 213 #define SUNXI_HDMI_PAD_CTRL0_RUN                0xfe800000
 214 #endif
 215
 216 #ifdef CONFIG_MACH_SUN4I
 217 #define SUNXI_HDMI_PAD_CTRL1                    0x00d8c820
 218 #elif defined CONFIG_MACH_SUN6I
 219 #define SUNXI_HDMI_PAD_CTRL1                    0x01ded030
 220 #else
 221 #define SUNXI_HDMI_PAD_CTRL1                    0x00d8c830
 222 #endif
 223 #define SUNXI_HDMI_PAD_CTRL1_HALVE              (1 << 6)
 224
 225 #ifdef CONFIG_MACH_SUN6I
 226 #define SUNXI_HDMI_PLL_CTRL                     0xba48a308
 227 #define SUNXI_HDMI_PLL_CTRL_DIV(n)              (((n) - 1) << 4)
 228 #else
 229 #define SUNXI_HDMI_PLL_CTRL                     0xfa4ef708
 230 #define SUNXI_HDMI_PLL_CTRL_DIV(n)              ((n) << 4)
 231 #endif
 232 #define SUNXI_HDMI_PLL_CTRL_DIV_MASK            (0xf << 4)
 233
 234 #define SUNXI_HDMI_PLL_DBG0_PLL3                (0 << 21)
 235 #define SUNXI_HDMI_PLL_DBG0_PLL7                (1 << 21)
 236
 237 #define SUNXI_HDMI_PKT_CTRL0                    0x00000f21
 238 #define SUNXI_HDMI_PKT_CTRL1                    0x0000000f
 239 #define SUNXI_HDMI_UNKNOWN_INPUT_SYNC           0x08000000
 240
 241 #ifdef CONFIG_MACH_SUN6I
 242 #define SUNXI_HMDI_DDC_CTRL_ENABLE              (1 << 0)
 243 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE          (1 << 4)
 244 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE          (1 << 6)
 245 #define SUNXI_HMDI_DDC_CTRL_START               (1 << 27)
 246 #define SUNXI_HMDI_DDC_CTRL_RESET               (1 << 31)
 247 #else
 248 #define SUNXI_HMDI_DDC_CTRL_RESET               (1 << 0)
 249 /* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
 250 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE          0
 251 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE          0
 252 #define SUNXI_HMDI_DDC_CTRL_START               (1 << 30)
 253 #define SUNXI_HMDI_DDC_CTRL_ENABLE              (1 << 31)
 254 #endif
 255
 256 #ifdef CONFIG_MACH_SUN6I
 257 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR          (0xa0 << 0)
 258 #else
 259 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR          (0x50 << 0)
 260 #endif
 261 #define SUNXI_HMDI_DDC_ADDR_OFFSET(n)           (((n) & 0xff) << 8)
 262 #define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR           (0x60 << 16)
 263 #define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n)     ((n) << 24)
 264
 265 #ifdef CONFIG_MACH_SUN6I
 266 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR          (1 << 15)
 267 #else
 268 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR          (1 << 31)
 269 #endif
 270
 271 #define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ  6
 272 #define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ  7
 273
 274 #ifdef CONFIG_MACH_SUN6I
 275 #define SUNXI_HDMI_DDC_CLOCK                    0x61
 276 #else
 277 /* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
 278 #define SUNXI_HDMI_DDC_CLOCK                    0x0d
 279 #endif
 280
 281 #define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE     (1 << 8)
 282 #define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE     (1 << 9)
 283
 284 int sunxi_simplefb_setup(void *blob);
 285
 286 #endif /* _SUNXI_DISPLAY_H */