2 * Sunxi platform display controller register and constant defines
4 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _SUNXI_DISPLAY_H
10 #define _SUNXI_DISPLAY_H
12 struct sunxi_de_be_reg {
13 u8 res0[0x800]; /* 0x000 */
15 u32 backcolor; /* 0x804 */
16 u32 disp_size; /* 0x808 */
17 u8 res1[0x4]; /* 0x80c */
18 u32 layer0_size; /* 0x810 */
19 u32 layer1_size; /* 0x814 */
20 u32 layer2_size; /* 0x818 */
21 u32 layer3_size; /* 0x81c */
22 u32 layer0_pos; /* 0x820 */
23 u32 layer1_pos; /* 0x824 */
24 u32 layer2_pos; /* 0x828 */
25 u32 layer3_pos; /* 0x82c */
26 u8 res2[0x10]; /* 0x830 */
27 u32 layer0_stride; /* 0x840 */
28 u32 layer1_stride; /* 0x844 */
29 u32 layer2_stride; /* 0x848 */
30 u32 layer3_stride; /* 0x84c */
31 u32 layer0_addr_low32b; /* 0x850 */
32 u32 layer1_addr_low32b; /* 0x854 */
33 u32 layer2_addr_low32b; /* 0x858 */
34 u32 layer3_addr_low32b; /* 0x85c */
35 u32 layer0_addr_high4b; /* 0x860 */
36 u32 layer1_addr_high4b; /* 0x864 */
37 u32 layer2_addr_high4b; /* 0x868 */
38 u32 layer3_addr_high4b; /* 0x86c */
39 u32 reg_ctrl; /* 0x870 */
40 u8 res3[0xc]; /* 0x874 */
41 u32 color_key_max; /* 0x880 */
42 u32 color_key_min; /* 0x884 */
43 u32 color_key_config; /* 0x888 */
44 u8 res4[0x4]; /* 0x88c */
45 u32 layer0_attr0_ctrl; /* 0x890 */
46 u32 layer1_attr0_ctrl; /* 0x894 */
47 u32 layer2_attr0_ctrl; /* 0x898 */
48 u32 layer3_attr0_ctrl; /* 0x89c */
49 u32 layer0_attr1_ctrl; /* 0x8a0 */
50 u32 layer1_attr1_ctrl; /* 0x8a4 */
51 u32 layer2_attr1_ctrl; /* 0x8a8 */
52 u32 layer3_attr1_ctrl; /* 0x8ac */
55 struct sunxi_lcdc_reg {
59 u8 res0[0x04]; /* 0x0c */
60 u32 tcon0_frm_ctrl; /* 0x10 */
61 u32 tcon0_frm_seed[6]; /* 0x14 */
62 u32 tcon0_frm_table[4]; /* 0x2c */
63 u8 res1[4]; /* 0x3c */
64 u32 tcon0_ctrl; /* 0x40 */
65 u32 tcon0_dclk; /* 0x44 */
66 u32 tcon0_timing_active; /* 0x48 */
67 u32 tcon0_timing_h; /* 0x4c */
68 u32 tcon0_timing_v; /* 0x50 */
69 u32 tcon0_timing_sync; /* 0x54 */
70 u32 tcon0_hv_intf; /* 0x58 */
71 u8 res2[0x04]; /* 0x5c */
72 u32 tcon0_cpu_intf; /* 0x60 */
73 u32 tcon0_cpu_wr_dat; /* 0x64 */
74 u32 tcon0_cpu_rd_dat0; /* 0x68 */
75 u32 tcon0_cpu_rd_dat1; /* 0x6c */
76 u32 tcon0_ttl_timing0; /* 0x70 */
77 u32 tcon0_ttl_timing1; /* 0x74 */
78 u32 tcon0_ttl_timing2; /* 0x78 */
79 u32 tcon0_ttl_timing3; /* 0x7c */
80 u32 tcon0_ttl_timing4; /* 0x80 */
81 u32 tcon0_lvds_intf; /* 0x84 */
82 u32 tcon0_io_polarity; /* 0x88 */
83 u32 tcon0_io_tristate; /* 0x8c */
84 u32 tcon1_ctrl; /* 0x90 */
85 u32 tcon1_timing_source; /* 0x94 */
86 u32 tcon1_timing_scale; /* 0x98 */
87 u32 tcon1_timing_out; /* 0x9c */
88 u32 tcon1_timing_h; /* 0xa0 */
89 u32 tcon1_timing_v; /* 0xa4 */
90 u32 tcon1_timing_sync; /* 0xa8 */
91 u8 res3[0x44]; /* 0xac */
92 u32 tcon1_io_polarity; /* 0xf0 */
93 u32 tcon1_io_tristate; /* 0xf4 */
96 struct sunxi_hdmi_reg {
97 u32 version_id; /* 0x000 */
101 u32 video_ctrl; /* 0x010 */
102 u32 video_size; /* 0x014 */
103 u32 video_bp; /* 0x018 */
104 u32 video_fp; /* 0x01c */
105 u32 video_spw; /* 0x020 */
106 u32 video_polarity; /* 0x024 */
107 u8 res0[0x58]; /* 0x028 */
108 u8 avi_info_frame[0x14]; /* 0x080 */
109 u8 res1[0x4c]; /* 0x094 */
110 u32 qcp_packet0; /* 0x0e0 */
111 u32 qcp_packet1; /* 0x0e4 */
112 u8 res2[0x118]; /* 0x0e8 */
113 u32 pad_ctrl0; /* 0x200 */
114 u32 pad_ctrl1; /* 0x204 */
115 u32 pll_ctrl; /* 0x208 */
116 u32 pll_dbg0; /* 0x20c */
117 u32 pll_dbg1; /* 0x210 */
118 u32 hpd_cec; /* 0x214 */
119 u8 res3[0x28]; /* 0x218 */
120 u8 vendor_info_frame[0x14]; /* 0x240 */
121 u8 res4[0x9c]; /* 0x254 */
122 u32 pkt_ctrl0; /* 0x2f0 */
123 u32 pkt_ctrl1; /* 0x2f4 */
124 u8 res5[0x8]; /* 0x2f8 */
125 u32 unknown; /* 0x300 */
126 u8 res6[0xc]; /* 0x304 */
127 u32 audio_sample_count; /* 0x310 */
128 u8 res7[0xec]; /* 0x314 */
129 u32 audio_tx_fifo; /* 0x400 */
130 u8 res8[0xfc]; /* 0x404 */
131 #ifndef CONFIG_MACH_SUN6I
132 u32 ddc_ctrl; /* 0x500 */
133 u32 ddc_addr; /* 0x504 */
134 u32 ddc_int_mask; /* 0x508 */
135 u32 ddc_int_status; /* 0x50c */
136 u32 ddc_fifo_ctrl; /* 0x510 */
137 u32 ddc_fifo_status; /* 0x514 */
138 u32 ddc_fifo_data; /* 0x518 */
139 u32 ddc_byte_count; /* 0x51c */
140 u32 ddc_cmnd; /* 0x520 */
141 u32 ddc_exreg; /* 0x524 */
142 u32 ddc_clock; /* 0x528 */
143 u8 res9[0x14]; /* 0x52c */
144 u32 ddc_line_ctrl; /* 0x540 */
146 u32 ddc_ctrl; /* 0x500 */
147 u32 ddc_exreg; /* 0x504 */
148 u32 ddc_cmnd; /* 0x508 */
149 u32 ddc_addr; /* 0x50c */
150 u32 ddc_int_mask; /* 0x510 */
151 u32 ddc_int_status; /* 0x514 */
152 u32 ddc_fifo_ctrl; /* 0x518 */
153 u32 ddc_fifo_status; /* 0x51c */
154 u32 ddc_clock; /* 0x520 */
155 u32 ddc_timeout; /* 0x524 */
156 u8 res9[0x18]; /* 0x528 */
157 u32 ddc_dbg; /* 0x540 */
158 u8 res10[0x3c]; /* 0x544 */
159 u32 ddc_fifo_data; /* 0x580 */
164 * DE-BE register constants.
166 #define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
167 #define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16)
168 #define SUNXI_DE_BE_MODE_ENABLE (1 << 0)
169 #define SUNXI_DE_BE_MODE_START (1 << 1)
170 #define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
171 #define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
172 #define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
173 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
176 * LCDC register constants.
178 #define SUNXI_LCDC_X(x) (((x) - 1) << 16)
179 #define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
180 #define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
181 #define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
182 #define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
183 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
184 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
185 #define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
186 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
187 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
188 #define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
189 #define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
190 #define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
191 #define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
192 #define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
193 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
194 #define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
195 #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
196 #define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
197 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
198 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
199 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
200 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
201 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
202 #define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
203 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
204 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
205 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
206 #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16)
209 * HDMI register constants.
211 #define SUNXI_HDMI_X(x) (((x) - 1) << 0)
212 #define SUNXI_HDMI_Y(y) (((y) - 1) << 16)
213 #define SUNXI_HDMI_CTRL_ENABLE (1 << 31)
214 #define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0)
215 #define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1)
216 #define SUNXI_HDMI_IRQ_STATUS_BITS 0x73
217 #define SUNXI_HDMI_HPD_DETECT (1 << 0)
218 #define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31)
219 #define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30)
220 #define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0)
221 #define SUNXI_HDMI_VIDEO_POL_VER (1 << 1)
222 #define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16)
223 #define SUNXI_HDMI_QCP_PACKET0 3
224 #define SUNXI_HDMI_QCP_PACKET1 0
226 #ifdef CONFIG_MACH_SUN6I
227 #define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f
228 #define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff
230 #define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000
231 #define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000
234 #ifdef CONFIG_MACH_SUN4I
235 #define SUNXI_HDMI_PAD_CTRL1 0x00d8c820
236 #elif defined CONFIG_MACH_SUN6I
237 #define SUNXI_HDMI_PAD_CTRL1 0x01ded030
239 #define SUNXI_HDMI_PAD_CTRL1 0x00d8c830
241 #define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6)
243 #ifdef CONFIG_MACH_SUN6I
244 #define SUNXI_HDMI_PLL_CTRL 0xba48a308
245 #define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4)
247 #define SUNXI_HDMI_PLL_CTRL 0xfa4ef708
248 #define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4)
250 #define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4)
252 #define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
253 #define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
255 #define SUNXI_HDMI_PKT_CTRL0 0x00000f21
256 #define SUNXI_HDMI_PKT_CTRL1 0x0000000f
257 #define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000
259 #ifdef CONFIG_MACH_SUN6I
260 #define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0)
261 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4)
262 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6)
263 #define SUNXI_HMDI_DDC_CTRL_START (1 << 27)
264 #define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31)
266 #define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0)
267 /* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
268 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0
269 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0
270 #define SUNXI_HMDI_DDC_CTRL_START (1 << 30)
271 #define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31)
274 #ifdef CONFIG_MACH_SUN6I
275 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0)
277 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0)
279 #define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8)
280 #define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16)
281 #define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24)
283 #ifdef CONFIG_MACH_SUN6I
284 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15)
286 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31)
289 #define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6
290 #define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7
292 #ifdef CONFIG_MACH_SUN6I
293 #define SUNXI_HDMI_DDC_CLOCK 0x61
295 /* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
296 #define SUNXI_HDMI_DDC_CLOCK 0x0d
299 #define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8)
300 #define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9)
302 int sunxi_simplefb_setup(void *blob);
304 #endif /* _SUNXI_DISPLAY_H */