1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * sun6i clock register definitions
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
10 #ifndef _SUNXI_CLOCK_SUN6I_H
11 #define _SUNXI_CLOCK_SUN6I_H
13 struct sunxi_ccm_reg {
14 u32 pll1_cfg; /* 0x00 pll1 control */
16 u32 pll2_cfg; /* 0x08 pll2 control */
18 u32 pll3_cfg; /* 0x10 pll3 control */
20 u32 pll4_cfg; /* 0x18 pll4 control */
22 u32 pll5_cfg; /* 0x20 pll5 control */
24 u32 pll6_cfg; /* 0x28 pll6 control */
26 u32 pll7_cfg; /* 0x30 pll7 control */
27 u32 sata_pll_cfg; /* 0x34 SATA pll control (R40 only) */
28 u32 pll8_cfg; /* 0x38 pll8 control */
30 u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
31 u32 pll9_cfg; /* 0x44 pll9 control */
32 u32 pll10_cfg; /* 0x48 pll10 control */
33 u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */
34 u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
35 u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
36 u32 apb2_div; /* 0x58 APB2 divide ratio */
37 u32 axi_gate; /* 0x5c axi module clock gating */
38 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
39 u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
40 u32 apb1_gate; /* 0x68 apb1 module clock gating */
41 u32 apb2_gate; /* 0x6c apb2 module clock gating */
42 u32 bus_gate4; /* 0x70 gate 4 module clock gating */
44 u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
45 u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
46 u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
47 u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
48 u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
49 u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
50 u32 ts_clk_cfg; /* 0x98 transport stream clock control */
51 u32 ss_clk_cfg; /* 0x9c security system clock control */
52 u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
53 u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
54 u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */
55 u32 spi3_clk_cfg; /* 0xac spi3 clock control */
56 u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/
57 u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
59 u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
61 u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */
62 u32 usb_clk_cfg; /* 0xcc USB clock control */
63 u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
65 u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
66 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
67 u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */
68 u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
69 u32 dram_clk_gate; /* 0x100 DRAM module gating */
70 #ifdef CONFIG_SUNXI_DE2
71 u32 de_clk_cfg; /* 0x104 DE module clock */
73 u32 be0_clk_cfg; /* 0x104 BE0 module clock */
75 u32 be1_clk_cfg; /* 0x108 BE1 module clock */
76 u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
77 u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
78 u32 mp_clk_cfg; /* 0x114 MP module clock */
79 #ifdef CONFIG_SUNXI_DE2
80 u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */
81 u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */
83 u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
84 u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
86 u32 tve_clk_cfg; /* 0x120 H3/H5 TVE module clock */
88 u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
89 u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
90 u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */
91 u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */
92 u32 ve_clk_cfg; /* 0x13c VE module clock */
93 u32 adda_clk_cfg; /* 0x140 ADDA module clock */
94 u32 avs_clk_cfg; /* 0x144 AVS module clock */
95 u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
97 u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
98 #ifdef CONFIG_SUNXI_DE2
99 u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */
101 u32 ps_clk_cfg; /* 0x154 PS module clock */
103 u32 mtc_clk_cfg; /* 0x158 MTC module clock */
104 u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
105 u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
107 u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
108 u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
110 u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */
111 u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */
112 u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */
113 u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */
115 u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
116 u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
117 u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */
119 u32 pll_lock; /* 0x200 PLL Lock Time */
120 u32 pll1_lock; /* 0x204 PLL1 Lock Time */
122 u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
123 u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
124 u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
125 u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
126 u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
127 u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
128 u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
129 u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */
130 u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
131 u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
132 u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
134 u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */
136 u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
137 u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
138 u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
139 u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
140 u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
141 u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
142 u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
143 u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */
144 u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
145 u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
146 u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
147 u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */
148 u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */
150 u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
151 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
152 u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
154 u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
156 u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
158 u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
160 u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */
164 #define APB2_CLK_SRC_LOSC (0x0 << 24)
165 #define APB2_CLK_SRC_OSC24M (0x1 << 24)
166 #define APB2_CLK_SRC_PLL6 (0x2 << 24)
167 #define APB2_CLK_SRC_MASK (0x3 << 24)
168 #define APB2_CLK_RATE_N_1 (0x0 << 16)
169 #define APB2_CLK_RATE_N_2 (0x1 << 16)
170 #define APB2_CLK_RATE_N_4 (0x2 << 16)
171 #define APB2_CLK_RATE_N_8 (0x3 << 16)
172 #define APB2_CLK_RATE_N_MASK (3 << 16)
173 #define APB2_CLK_RATE_M(m) (((m)-1) << 0)
174 #define APB2_CLK_RATE_M_MASK (0x1f << 0)
176 /* apb2 gate field */
177 #define APB2_GATE_UART_SHIFT (16)
178 #define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
179 #define APB2_GATE_TWI_SHIFT (0)
180 #define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
182 /* cpu_axi_cfg bits */
183 #define AXI_DIV_SHIFT 0
184 #define ATB_DIV_SHIFT 8
185 #define CPU_CLK_SRC_SHIFT 16
195 #define CPU_CLK_SRC_OSC24M 1
196 #define CPU_CLK_SRC_PLL1 2
198 #define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
199 #define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
200 #define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
201 #define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16)
202 #define CCM_PLL1_CTRL_EN (0x1 << 31)
204 #define CCM_PLL3_CTRL_M_SHIFT 0
205 #define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT)
206 #define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
207 #define CCM_PLL3_CTRL_N_SHIFT 8
208 #define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT)
209 #define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
210 #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
211 #define CCM_PLL3_CTRL_LOCK (0x1 << 28)
212 #define CCM_PLL3_CTRL_EN (0x1 << 31)
214 #define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
215 #define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
216 #define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
217 #define CCM_PLL5_CTRL_UPD (0x1 << 20)
218 #define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
219 #define CCM_PLL5_CTRL_EN (0x1 << 31)
221 #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
223 #define CCM_PLL6_CTRL_N_SHIFT 8
224 #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
225 #define CCM_PLL6_CTRL_K_SHIFT 4
226 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
227 #define CCM_PLL6_CTRL_LOCK (1 << 28)
229 #define CCM_SATA_PLL_DEFAULT 0x90005811 /* 100 MHz */
231 #define CCM_MIPI_PLL_CTRL_M_SHIFT 0
232 #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
233 #define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
234 #define CCM_MIPI_PLL_CTRL_K_SHIFT 4
235 #define CCM_MIPI_PLL_CTRL_K_MASK (0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT)
236 #define CCM_MIPI_PLL_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
237 #define CCM_MIPI_PLL_CTRL_N_SHIFT 8
238 #define CCM_MIPI_PLL_CTRL_N_MASK (0xf << CCM_MIPI_PLL_CTRL_N_SHIFT)
239 #define CCM_MIPI_PLL_CTRL_N(n) ((((n) - 1) & 0xf) << 8)
240 #define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22)
241 #define CCM_MIPI_PLL_CTRL_EN (0x1 << 31)
243 #define CCM_PLL10_CTRL_M_SHIFT 0
244 #define CCM_PLL10_CTRL_M_MASK (0xf << CCM_PLL10_CTRL_M_SHIFT)
245 #define CCM_PLL10_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
246 #define CCM_PLL10_CTRL_N_SHIFT 8
247 #define CCM_PLL10_CTRL_N_MASK (0x7f << CCM_PLL10_CTRL_N_SHIFT)
248 #define CCM_PLL10_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
249 #define CCM_PLL10_CTRL_INTEGER_MODE (0x1 << 24)
250 #define CCM_PLL10_CTRL_LOCK (0x1 << 28)
251 #define CCM_PLL10_CTRL_EN (0x1 << 31)
253 #define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8)
254 #define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24)
255 #define CCM_PLL11_CTRL_UPD (0x1 << 30)
256 #define CCM_PLL11_CTRL_EN (0x1 << 31)
258 #define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24)
259 #define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7)
260 #define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16)
261 #define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f)
263 #if defined(CONFIG_MACH_SUN50I)
264 /* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
265 #define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
267 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
270 #define AXI_GATE_OFFSET_DRAM 0
272 /* ahb_gate0 offsets */
273 #ifdef CONFIG_MACH_SUNXI_H3_H5
275 * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
276 * them 0 - 2 like they were called on older SoCs.
278 #define AHB_GATE_OFFSET_USB_OHCI3 31
279 #define AHB_GATE_OFFSET_USB_OHCI2 30
280 #define AHB_GATE_OFFSET_USB_OHCI1 29
281 #define AHB_GATE_OFFSET_USB_OHCI0 28
282 #define AHB_GATE_OFFSET_USB_EHCI3 27
283 #define AHB_GATE_OFFSET_USB_EHCI2 26
284 #define AHB_GATE_OFFSET_USB_EHCI1 25
285 #define AHB_GATE_OFFSET_USB_EHCI0 24
286 #elif defined(CONFIG_MACH_SUN50I)
287 #define AHB_GATE_OFFSET_USB_OHCI0 28
288 #define AHB_GATE_OFFSET_USB_OHCI1 29
289 #define AHB_GATE_OFFSET_USB_EHCI0 24
290 #define AHB_GATE_OFFSET_USB_EHCI1 25
292 #define AHB_GATE_OFFSET_USB_OHCI1 30
293 #define AHB_GATE_OFFSET_USB_OHCI0 29
294 #define AHB_GATE_OFFSET_USB_EHCI1 27
295 #define AHB_GATE_OFFSET_USB_EHCI0 26
297 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5)
298 #define AHB_GATE_OFFSET_USB0 23
299 #elif !defined(CONFIG_MACH_SUN8I_R40)
300 #define AHB_GATE_OFFSET_USB0 24
302 #define AHB_GATE_OFFSET_USB0 25
303 #define AHB_GATE_OFFSET_SATA 24
305 #define AHB_GATE_OFFSET_MCTL 14
306 #define AHB_GATE_OFFSET_GMAC 17
307 #define AHB_GATE_OFFSET_NAND0 13
308 #define AHB_GATE_OFFSET_NAND1 12
309 #define AHB_GATE_OFFSET_MMC3 11
310 #define AHB_GATE_OFFSET_MMC2 10
311 #define AHB_GATE_OFFSET_MMC1 9
312 #define AHB_GATE_OFFSET_MMC0 8
313 #define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
314 #define AHB_GATE_OFFSET_DMA 6
315 #define AHB_GATE_OFFSET_SS 5
317 /* ahb_gate1 offsets */
318 #define AHB_GATE_OFFSET_DRC0 25
319 #define AHB_GATE_OFFSET_DE_FE0 14
320 #define AHB_GATE_OFFSET_DE_BE0 12
321 #define AHB_GATE_OFFSET_DE 12
322 #define AHB_GATE_OFFSET_HDMI 11
323 #define AHB_GATE_OFFSET_TVE 9
324 #ifndef CONFIG_SUNXI_DE2
325 #define AHB_GATE_OFFSET_LCD1 5
326 #define AHB_GATE_OFFSET_LCD0 4
328 #define AHB_GATE_OFFSET_LCD1 4
329 #define AHB_GATE_OFFSET_LCD0 3
332 #define CCM_NAND_CTRL_M(x) ((x) - 1)
333 #define CCM_NAND_CTRL_N(x) ((x) << 16)
334 #define CCM_NAND_CTRL_PLL6 (0x1 << 24)
335 #define CCM_NAND_CTRL_ENABLE (0x1 << 31)
337 #define CCM_MMC_CTRL_M(x) ((x) - 1)
338 #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
339 #define CCM_MMC_CTRL_N(x) ((x) << 16)
340 #define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
341 #define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
342 #define CCM_MMC_CTRL_PLL6 (0x1 << 24)
343 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
345 #define CCM_SATA_CTRL_ENABLE (0x1 << 31)
346 #define CCM_SATA_CTRL_USE_EXTCLK (0x1 << 24)
348 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
349 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
350 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
351 #define CCM_USB_CTRL_PHY3_RST (0x1 << 3)
352 /* There is no global phy clk gate on sun6i, define as 0 */
353 #define CCM_USB_CTRL_PHYGATE 0
354 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
355 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
356 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
357 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
358 #ifdef CONFIG_MACH_SUNXI_H3_H5
359 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
360 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
361 #define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
362 #define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
364 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
365 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
368 #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
369 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
370 #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
371 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
372 #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
373 #define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
374 #define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
376 #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
378 #define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0)
379 #define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0)
380 #define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
381 #define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
382 #define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20)
383 #define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
384 #define CCM_DRAMCLK_CFG_SRC_PLL11 (0x1 << 20) /* A64 only */
385 #define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20)
386 #define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
387 #define CCM_DRAMCLK_CFG_RST (0x1 << 31)
389 #define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
390 #define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */
391 #define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16)
393 #define CCM_MBUS_RESET_RESET (0x1 << 31)
395 #define CCM_DRAM_GATE_OFFSET_DE_FE0 24
396 #define CCM_DRAM_GATE_OFFSET_DE_FE1 25
397 #define CCM_DRAM_GATE_OFFSET_DE_BE0 26
398 #define CCM_DRAM_GATE_OFFSET_DE_BE1 27
400 #define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
401 #define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
402 #define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
403 #define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
404 #define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24)
405 /* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */
406 #define CCM_LCD_CH0_CTRL_RST 0
407 #define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
409 #define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
410 #define CCM_LCD_CH1_CTRL_HALF_SCLK1 0 /* no seperate sclk1 & 2 on sun6i */
411 #define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
412 #define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
413 #define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
414 #define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
415 #define CCM_LCD_CH1_CTRL_GATE (0x1 << 31)
417 #define CCM_LCD0_CTRL_GATE (0x1 << 31)
418 #define CCM_LCD0_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
420 #define CCM_LCD1_CTRL_GATE (0x1 << 31)
421 #define CCM_LCD1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
423 #define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
424 #define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
425 #define CCM_HDMI_CTRL_PLL3 (0 << 24)
426 #define CCM_HDMI_CTRL_PLL7 (1 << 24)
427 #define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
428 #define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
429 #define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
430 #define CCM_HDMI_CTRL_GATE (0x1 << 31)
432 #define CCM_HDMI_SLOW_CTRL_DDC_GATE (1 << 31)
434 #define CCM_TVE_CTRL_GATE (0x1 << 31)
435 #define CCM_TVE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
437 #if defined(CONFIG_MACH_SUN50I)
438 #define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */
439 #elif defined(CONFIG_MACH_SUN8I)
440 #define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
442 #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
444 #define MBUS_CLK_GATE (0x1 << 31)
446 #define CCM_PLL5_PATTERN 0xd1303333
447 #define CCM_PLL11_PATTERN 0xf5860000
449 /* ahb_reset0 offsets */
450 #ifdef CONFIG_MACH_SUN8I_R40
451 #define AHB_RESET_OFFSET_SATA 24
453 #define AHB_RESET_OFFSET_GMAC 17
454 #define AHB_RESET_OFFSET_MCTL 14
455 #define AHB_RESET_OFFSET_MMC3 11
456 #define AHB_RESET_OFFSET_MMC2 10
457 #define AHB_RESET_OFFSET_MMC1 9
458 #define AHB_RESET_OFFSET_MMC0 8
459 #define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
460 #define AHB_RESET_OFFSET_SS 5
462 /* ahb_reset1 offsets */
463 #define AHB_RESET_OFFSET_SAT 26
464 #define AHB_RESET_OFFSET_DRC0 25
465 #define AHB_RESET_OFFSET_DE_FE0 14
466 #define AHB_RESET_OFFSET_DE_BE0 12
467 #define AHB_RESET_OFFSET_DE 12
468 #define AHB_RESET_OFFSET_HDMI 11
469 #define AHB_RESET_OFFSET_HDMI2 10
470 #define AHB_RESET_OFFSET_TVE 9
471 #ifndef CONFIG_SUNXI_DE2
472 #define AHB_RESET_OFFSET_LCD1 5
473 #define AHB_RESET_OFFSET_LCD0 4
475 #define AHB_RESET_OFFSET_LCD1 4
476 #define AHB_RESET_OFFSET_LCD0 3
479 /* ahb_reset2 offsets */
480 #define AHB_RESET_OFFSET_EPHY 2
481 #define AHB_RESET_OFFSET_LVDS 0
484 #define APB2_RESET_UART_SHIFT (16)
485 #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
486 #define APB2_RESET_TWI_SHIFT (0)
487 #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
489 /* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
490 #define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
491 #define CCM_DE_CTRL_PLL_MASK (0xf << 24)
492 #define CCM_DE_CTRL_PLL3 (0 << 24)
493 #define CCM_DE_CTRL_PLL7 (1 << 24)
494 #define CCM_DE_CTRL_PLL6_2X (2 << 24)
495 #define CCM_DE_CTRL_PLL8 (3 << 24)
496 #define CCM_DE_CTRL_PLL9 (4 << 24)
497 #define CCM_DE_CTRL_PLL10 (5 << 24)
498 #define CCM_DE_CTRL_GATE (1 << 31)
500 /* CCM bits common to all Display Engine 2.0 clock ctrl regs */
501 #define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
502 #define CCM_DE2_CTRL_PLL_MASK (3 << 24)
503 #define CCM_DE2_CTRL_PLL6_2X (0 << 24)
504 #define CCM_DE2_CTRL_PLL10 (1 << 24)
505 #define CCM_DE2_CTRL_GATE (0x1 << 31)
507 /* CCU security switch, H3 only */
508 #define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
509 #define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
510 #define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0)
513 void clock_set_pll1(unsigned int hz);
514 void clock_set_pll3(unsigned int hz);
515 void clock_set_pll3_factors(int m, int n);
516 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
517 void clock_set_pll10(unsigned int hz);
518 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
519 void clock_set_mipi_pll(unsigned int hz);
520 unsigned int clock_get_pll3(void);
521 unsigned int clock_get_pll6(void);
522 unsigned int clock_get_mipi_pll(void);
525 #endif /* _SUNXI_CLOCK_SUN6I_H */