arch/arm/include/asm/arch-stm32f7/stm32_pwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #ifndef __STM32_PWR_H_
   8
   9 /*
  10  * Offsets of some PWR registers
  11  */
  12 #define PWR_CR1_ODEN                    BIT(16)
  13 #define PWR_CR1_ODSWEN                  BIT(17)
  14 #define PWR_CSR1_ODRDY                  BIT(16)
  15 #define PWR_CSR1_ODSWRDY                BIT(17)
  16
  17 struct stm32_pwr_regs {
  18         u32 cr1;   /* power control register 1 */
  19         u32 csr1;  /* power control/status register 2 */
  20         u32 cr2;   /* power control register 2 */
  21         u32 csr2;  /* power control/status register 2 */
  22 };
  23
  24 #endif /* __STM32_PWR_H_ */