2 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_ARCH_HARDWARE_H
9 #define _ASM_ARCH_HARDWARE_H
12 #define ITCM_FLASH_BASE 0x00200000UL
13 #define AXIM_FLASH_BASE 0x08000000UL
15 #define ITCM_SRAM_BASE 0x00000000UL
16 #define DTCM_SRAM_BASE 0x20000000UL
17 #define SRAM1_BASE 0x20010000UL
18 #define SRAM2_BASE 0x2004C000UL
20 #define PERIPH_BASE 0x40000000UL
22 #define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
23 #define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000)
24 #define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000)
25 #define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000)
26 #define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000)
28 #define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
29 #define USART2_BASE (APB1_PERIPH_BASE + 0x4400)
30 #define USART3_BASE (APB1_PERIPH_BASE + 0x4800)
31 #define PWR_BASE (APB1_PERIPH_BASE + 0x7000)
33 #define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
34 #define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
35 #define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800)
37 #define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
38 #define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
39 #define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800)
40 #define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00)
41 #define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000)
42 #define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400)
43 #define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800)
44 #define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00)
45 #define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000)
46 #define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400)
47 #define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800)
48 #define RCC_BASE (AHB1_PERIPH_BASE + 0x3800)
49 #define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
52 #define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x40000140)
54 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
55 [0 ... 3] = 32 * 1024,
57 [5 ... 7] = 256 * 1024
60 #define STM32_BUS_MASK GENMASK(31, 16)
62 struct stm32_rcc_regs {
63 u32 cr; /* RCC clock control */
64 u32 pllcfgr; /* RCC PLL configuration */
65 u32 cfgr; /* RCC clock configuration */
66 u32 cir; /* RCC clock interrupt */
67 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
68 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
69 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
71 u32 apb1rstr; /* RCC APB1 peripheral reset */
72 u32 apb2rstr; /* RCC APB2 peripheral reset */
74 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
75 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
76 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
78 u32 apb1enr; /* RCC APB1 peripheral clock enable */
79 u32 apb2enr; /* RCC APB2 peripheral clock enable */
81 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
82 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
83 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
85 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
86 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
88 u32 bdcr; /* RCC Backup domain control */
89 u32 csr; /* RCC clock control & status */
91 u32 sscgr; /* RCC spread spectrum clock generation */
92 u32 plli2scfgr; /* RCC PLLI2S configuration */
93 u32 pllsaicfgr; /* PLLSAI configuration */
94 u32 dckcfgr; /* dedicated clocks configuration register */
96 #define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
98 struct stm32_pwr_regs {
99 u32 cr1; /* power control register 1 */
100 u32 csr1; /* power control/status register 2 */
101 u32 cr2; /* power control register 2 */
102 u32 csr2; /* power control/status register 2 */
104 #define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
106 void stm32_flash_latency_cfg(int latency);
108 #endif /* _ASM_ARCH_HARDWARE_H */