3 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
6 * Kamil Lulko, <rev13@wp.pl>
8 * SPDX-License-Identifier: GPL-2.0+
14 struct stm32_fmc_regs {
15 u32 sdcr1; /* Control register 1 */
16 u32 sdcr2; /* Control register 2 */
17 u32 sdtr1; /* Timing register 1 */
18 u32 sdtr2; /* Timing register 2 */
19 u32 sdcmr; /* Mode register */
20 u32 sdrtr; /* Refresh timing register */
21 u32 sdsr; /* Status register */
27 #define STM32_SDRAM_FMC_BASE 0xA0000140
28 #define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
30 /* Control register SDCR */
31 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
32 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
33 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
34 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
35 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
36 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
37 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
38 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
39 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
41 /* Timings register SDTR */
42 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
43 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
44 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
45 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
46 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
47 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
48 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
51 #define FMC_SDCMR_NRFS_SHIFT 5
53 #define FMC_SDCMR_MODE_NORMAL 0
54 #define FMC_SDCMR_MODE_START_CLOCK 1
55 #define FMC_SDCMR_MODE_PRECHARGE 2
56 #define FMC_SDCMR_MODE_AUTOREFRESH 3
57 #define FMC_SDCMR_MODE_WRITE_MODE 4
58 #define FMC_SDCMR_MODE_SELFREFRESH 5
59 #define FMC_SDCMR_MODE_POWERDOWN 6
61 #define FMC_SDCMR_BANK_1 (1 << 4)
62 #define FMC_SDCMR_BANK_2 (1 << 3)
64 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9
66 #define FMC_SDSR_BUSY (1 << 5)
68 #define FMC_BUSY_WAIT() do { \
69 __asm__ __volatile__ ("dsb" : : : "memory"); \
70 while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
75 #endif /* _MACH_FMC_H_ */