2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 * SPDX-License-Identifier: BSD-3-Clause
8 #ifndef _FPGA_MANAGER_H_
9 #define _FPGA_MANAGER_H_
13 struct socfpga_fpga_manager {
14 /* FPGA Manager Module */
22 u32 _pad_0x1c_0x82c[517];
24 /* Configuration Monitor (MON) Registers */
25 u32 gpio_inten; /* 0x830 */
27 u32 gpio_inttype_level;
28 u32 gpio_int_polarity;
29 u32 gpio_intstatus; /* 0x840 */
30 u32 gpio_raw_intstatus;
33 u32 gpio_ext_porta; /* 0x850 */
34 u32 _pad_0x854_0x85c[3];
35 u32 gpio_1s_sync; /* 0x860 */
36 u32 _pad_0x864_0x868[2];
38 u32 gpio_config_reg2; /* 0x870 */
42 #define FPGAMGRREGS_STAT_MODE_MASK 0x7
43 #define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
44 #define FPGAMGRREGS_STAT_MSEL_LSB 3
46 #define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
47 #define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
48 #define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
49 #define FPGAMGRREGS_CTRL_NCE_MASK 0x2
50 #define FPGAMGRREGS_CTRL_EN_MASK 0x1
51 #define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
53 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
54 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
55 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
56 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
59 #define FPGAMGRREGS_MODE_FPGAOFF 0x0
60 #define FPGAMGRREGS_MODE_RESETPHASE 0x1
61 #define FPGAMGRREGS_MODE_CFGPHASE 0x2
62 #define FPGAMGRREGS_MODE_INITPHASE 0x3
63 #define FPGAMGRREGS_MODE_USERMODE 0x4
64 #define FPGAMGRREGS_MODE_UNKNOWN 0x5
66 /* FPGA CD Ratio Value */
67 #define CDRATIO_x1 0x0
68 #define CDRATIO_x2 0x1
69 #define CDRATIO_x4 0x2
70 #define CDRATIO_x8 0x3
72 /* SoCFPGA support functions */
73 int fpgamgr_test_fpga_ready(void);
74 int fpgamgr_poll_fpga_ready(void);
75 int fpgamgr_get_mode(void);
77 #endif /* _FPGA_MANAGER_H_ */