2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CLOCK_MANAGER_H_
8 #define _CLOCK_MANAGER_H_
12 uint32_t main_vco_base;
17 uint32_t mainnandsdmmcclk;
18 uint32_t cfg2fuser0clk;
24 /* peripheral group */
25 uint32_t peri_vco_base;
29 uint32_t pernandsdmmcclk;
37 uint32_t sdram_vco_base;
44 extern void cm_basic_init(const cm_config_t *cfg);
46 struct socfpga_clock_manager {
53 u32 _pad_0x18_0x3f[10];
57 u32 _pad_0xe0_0x200[72];
63 u32 main_pll_dbgatclk;
64 u32 main_pll_mainqspiclk;
65 u32 main_pll_mainnandsdmmcclk;
66 u32 main_pll_cfgs2fuser0clk;
70 u32 main_pll_tracediv;
73 u32 main_pll__pad_0x38_0x40[2];
79 u32 per_pll_perqspiclk;
80 u32 per_pll_pernandsdmmcclk;
81 u32 per_pll_perbaseclk;
82 u32 per_pll_s2fuser1clk;
88 u32 per_pll__pad_0x34_0x40[3];
92 u32 sdr_pll_ddrdqsclk;
93 u32 sdr_pll_ddr2xdqsclk;
95 u32 sdr_pll_s2fuser2clk;
100 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
101 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
102 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
103 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
104 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
105 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
106 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
107 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
108 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
109 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
110 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
111 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
112 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
113 #define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
114 #define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
115 #define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
116 #define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
117 #define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
118 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
119 #define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
120 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
121 #define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
122 #define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
123 #define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
124 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
125 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
126 #define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
127 #define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
128 #define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
129 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
130 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
131 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
132 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
133 (((x) << 0) & 0x000001ff)
134 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
135 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
136 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
137 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
138 (((x) << 0) & 0x000001ff)
139 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
140 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
141 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
142 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
143 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
144 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
145 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
146 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
147 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
148 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
149 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
150 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
151 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
152 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
153 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
154 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
155 #define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
156 #define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
157 #define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
158 #define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
159 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
160 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
161 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
162 #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
163 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
164 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
165 #define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
166 #define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
167 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
168 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
169 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
170 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
171 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
172 #define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
173 #define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
174 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
175 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
176 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
177 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
178 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
179 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
180 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
181 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
182 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
183 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
184 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
185 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
186 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
187 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
188 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
189 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
191 #define MAIN_VCO_BASE \
192 (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
193 CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
195 #define PERI_VCO_BASE \
196 (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
197 CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
198 CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
200 #define SDR_VCO_BASE \
201 (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
202 CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
203 CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
205 #endif /* _CLOCK_MANAGER_H_ */