1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
5 #ifndef _ASM_ARCH_SDRAM_RK322X_H
6 #define _ASM_ARCH_SDRAM_RK322X_H
9 #include <linux/bitops.h>
12 struct rk322x_sdram_channel {
14 * bit width in address, eg:
15 * 8 banks using 3 bit to address,
16 * 2 cs using 1 bit to address.
26 #if CONFIG_IS_ENABLED(OF_PLATDATA)
28 * For of-platdata, which would otherwise convert this into two
29 * byte-swapped integers. With a size of 9 bytes, this struct will
30 * appear in of-platdata as a byte array.
32 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
38 struct rk322x_ddr_pctl {
43 u32 reserved0[(0x40 - 0x10) / 4];
49 u32 reserved1[(0x60 - 0x54) / 4];
53 u32 reserved2[(0x7c - 0x6c) / 4];
70 u32 reserved4[(0xc0 - 0xb4) / 4];
107 u32 reserved5[(0x180 - 0x14c) / 4];
112 u32 reserved6[(0x200 - 0x190) / 4];
129 /* dfi control registers */
134 /* dfi write data registers */
137 u32 reserved7[(0x260 - 0x258) / 4];
140 u32 reserved8[(0x270 - 0x268) / 4];
152 u32 reserved10[(0x2ac - 0x29c) / 4];
157 u32 dfitrrdlvlgateen;
167 u32 reserved12[(0x2f0 - 0x2e4) / 4];
170 u32 reserved13[(0x300 - 0x2f4) / 4];
177 u32 dfitrwrlvldelay0;
178 u32 dfitrwrlvldelay1;
179 u32 dfitrwrlvldelay2;
180 u32 dfitrrdlvldelay0;
181 u32 dfitrrdlvldelay1;
182 u32 dfitrrdlvldelay2;
183 u32 dfitrrdlvlgatedelay0;
184 u32 dfitrrdlvlgatedelay1;
185 u32 dfitrrdlvlgatedelay2;
187 u32 reserved14[(0x3f8 - 0x340) / 4];
191 check_member(rk322x_ddr_pctl, iptr, 0x03fc);
193 struct rk322x_ddr_phy {
194 u32 ddrphy_reg[0x100];
197 struct rk322x_pctl_timing {
235 struct rk322x_phy_timing {
242 struct rk322x_msch_timings {
250 struct rk322x_service_sys {
261 struct rk322x_base_params {
262 struct rk322x_msch_timings noc_timing;
274 #define DFI_INIT_START BIT(0)
275 #define DFI_DATA_BYTE_DISABLE_EN BIT(2)
278 #define DFI_DRAM_CLK_SR_EN BIT(0)
279 #define DFI_DRAM_CLK_DPD_EN BIT(1)
282 #define DFI_PARITY_INTR_EN BIT(0)
283 #define DFI_PARITY_EN BIT(1)
286 #define TLP_RESP_TIME_SHIFT 16
287 #define LP_SR_EN BIT(8)
288 #define LP_PD_EN BIT(0)
290 /* PCT_DFITCTRLDELAY */
291 #define TCTRL_DELAY_TIME_SHIFT 0
293 /* PCT_DFITPHYWRDATA */
294 #define TPHY_WRDATA_TIME_SHIFT 0
296 /* PCT_DFITPHYRDLAT */
297 #define TPHY_RDLAT_TIME_SHIFT 0
299 /* PCT_DFITDRAMCLKDIS */
300 #define TDRAM_CLK_DIS_TIME_SHIFT 0
302 /* PCT_DFITDRAMCLKEN */
303 #define TDRAM_CLK_EN_TIME_SHIFT 0
306 #define RANK0_ODT_WRITE_SEL BIT(3)
307 #define RANK1_ODT_WRITE_SEL BIT(11)
309 /* PCTL_DFIODTCFG1 */
310 #define ODT_LEN_BL8_W_SHIFT 16
313 #define ACDLLCR_DLLDIS BIT(31)
314 #define ACDLLCR_DLLSRST BIT(30)
317 #define DXDLLCR_DLLDIS BIT(31)
318 #define DXDLLCR_DLLSRST BIT(30)
321 #define DLLGCR_SBIAS BIT(30)
324 #define DQSRTT BIT(9)
325 #define DQRTT BIT(10)
328 #define PIR_INIT BIT(0)
329 #define PIR_DLLSRST BIT(1)
330 #define PIR_DLLLOCK BIT(2)
331 #define PIR_ZCAL BIT(3)
332 #define PIR_ITMSRST BIT(4)
333 #define PIR_DRAMRST BIT(5)
334 #define PIR_DRAMINIT BIT(6)
335 #define PIR_QSTRN BIT(7)
336 #define PIR_RVTRN BIT(8)
337 #define PIR_ICPC BIT(16)
338 #define PIR_DLLBYP BIT(17)
339 #define PIR_CTLDINIT BIT(18)
340 #define PIR_CLRSR BIT(28)
341 #define PIR_LOCKBYP BIT(29)
342 #define PIR_ZCALBYP BIT(30)
343 #define PIR_INITBYP BIT(31)
346 #define PGCR_DFTLMT_SHIFT 3
347 #define PGCR_DFTCMP_SHIFT 2
348 #define PGCR_DQSCFG_SHIFT 1
349 #define PGCR_ITMDMD_SHIFT 0
352 #define PGSR_IDONE BIT(0)
353 #define PGSR_DLDONE BIT(1)
354 #define PGSR_ZCDONE BIT(2)
355 #define PGSR_DIDONE BIT(3)
356 #define PGSR_DTDONE BIT(4)
357 #define PGSR_DTERR BIT(5)
358 #define PGSR_DTIERR BIT(6)
359 #define PGSR_DFTERR BIT(7)
360 #define PGSR_RVERR BIT(8)
361 #define PGSR_RVEIRR BIT(9)
364 #define PRT_ITMSRST_SHIFT 18
365 #define PRT_DLLLOCK_SHIFT 6
366 #define PRT_DLLSRST_SHIFT 0
369 #define PRT_DINIT0_SHIFT 0
370 #define PRT_DINIT1_SHIFT 19
373 #define PRT_DINIT2_SHIFT 0
374 #define PRT_DINIT3_SHIFT 17
377 #define DDRMD_LPDDR 0
381 #define DDRMD_LPDDR2_LPDDR3 4
383 #define DDRMD_SHIFT 0
388 #define DQSNRES_MASK 0xf
389 #define DQSNRES_SHIFT 8
390 #define DQSRES_MASK 0xf
391 #define DQSRES_SHIFT 4
394 #define TDQSCKMAX_SHIFT 27
395 #define TDQSCKMAX_MASK 7
396 #define TDQSCK_SHIFT 24
397 #define TDQSCK_MASK 7
400 #define DQSGX_SHIFT 5
402 #define DQSGE_SHIFT 8
409 #define SLEEP_STATE 3
410 #define WAKEUP_STATE 4
413 #define LP_TRIG_SHIFT 4
414 #define LP_TRIG_MASK 7
415 #define PCTL_STAT_MASK 7
422 #define LOW_POWER_ENTRY_REQ 6
423 #define LOW_POWER_EXIT_REQ 7
426 #define PD_OUTPUT_SHIFT 0
427 #define PU_OUTPUT_SHIFT 5
428 #define PD_ONDIE_SHIFT 10
429 #define PU_ONDIE_SHIFT 15
430 #define ZDEN_SHIFT 28
433 #define SBIAS_BYPASS BIT(23)
436 #define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
437 #define PD_IDLE_SHIFT 8
438 #define MDDR_EN (2 << 22)
439 #define LPDDR2_EN (3 << 22)
440 #define LPDDR3_EN (1 << 22)
441 #define DDR2_EN (0 << 5)
442 #define DDR3_EN (1 << 5)
443 #define LPDDR2_S2 (0 << 6)
444 #define LPDDR2_S4 (1 << 6)
445 #define MDDR_LPDDR2_BL_2 (0 << 20)
446 #define MDDR_LPDDR2_BL_4 (1 << 20)
447 #define MDDR_LPDDR2_BL_8 (2 << 20)
448 #define MDDR_LPDDR2_BL_16 (3 << 20)
449 #define DDR2_DDR3_BL_4 0
450 #define DDR2_DDR3_BL_8 1
451 #define TFAW_SHIFT 18
452 #define PD_EXIT_SLOW (0 << 17)
453 #define PD_EXIT_FAST (1 << 17)
454 #define PD_TYPE_SHIFT 16
455 #define BURSTLENGTH_SHIFT 20
458 #define POWER_UP_START BIT(0)
461 #define POWER_UP_DONE BIT(0)
476 #define BANK_ADDR_MASK 7
477 #define BANK_ADDR_SHIFT 17
478 #define CMD_ADDR_MASK 0x1fff
479 #define CMD_ADDR_SHIFT 4
481 #define LPDDR23_MA_SHIFT 4
482 #define LPDDR23_MA_MASK 0xff
483 #define LPDDR23_OP_SHIFT 12
484 #define LPDDR23_OP_MASK 0xff
486 #define START_CMD (1u << 31)
492 SOFT_DERESET_ANALOG = 1 << 2,
493 SOFT_DERESET_DIGITAL = 1 << 3,
494 SOFT_RESET_SHIFT = 2,
506 MEMORY_SELECT_DDR3 = 0 << 0,
507 MEMORY_SELECT_LPDDR3 = 2 << 0,
508 MEMORY_SELECT_LPDDR2 = 3 << 0,
509 DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4,
510 DQS_SQU_CAL_SEL_CS1 = 1 << 4,
511 DQS_SQU_CAL_SEL_CS0 = 2 << 4,
512 DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
513 DQS_SQU_CAL_BYPASS_MODE = 1 << 1,
514 DQS_SQU_CAL_START = 1 << 0,
515 DQS_SQU_NO_CAL = 0 << 0,
518 /* CK pull up/down driver strength control */
520 PHY_RON_RTT_DISABLE = 0,
521 PHY_RON_RTT_451OHM = 1,
527 PHY_RON_RTT_64OHM = 7,
529 PHY_RON_RTT_56OHM = 16,
536 PHY_RON_RTT_30OHM = 23,
538 PHY_RON_RTT_28OHM = 24,
545 PHY_RON_RTT_19OHM = 31,
548 /* DQS squelch DLL delay */
550 DQS_DLL_NO_DELAY = 0,
561 #define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0))
562 #define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0))
563 #define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7))
564 #define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7))
566 #define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8))
567 #define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8))
569 #define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6))
570 #define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6))
572 #define PHY_DRV_ODT_SET(n) (((n) << 4) | (n))
573 #define DDR3_DLL_RESET (1 << 8)
575 #endif /* _ASM_ARCH_SDRAM_RK322X_H */