1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd
6 #ifndef _ASM_ARCH_SDRAM_PHY_PX30_H
7 #define _ASM_ARCH_SDRAM_PHY_PX30_H
8 #include <asm/arch-rockchip/sdram_common.h>
9 #include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
15 #define PHY_REG(base, n) ((base) + 4 * (n))
18 #define DIGITAL_DERESET BIT(3)
19 #define ANALOG_DERESET BIT(2)
20 #define DIGITAL_RESET (0 << 3)
21 #define ANALOG_RESET (0 << 2)
25 #define PHY_LPDDR2 (1)
27 #define PHY_LPDDR3 (3)
29 #define PHY_BL_4 (0 << 2)
30 #define PHY_BL_8 BIT(2)
33 #define PHY_DTT_EN BIT(0)
34 #define PHY_DTT_DISB (0 << 0)
35 #define PHY_WRITE_LEVELING_EN BIT(2)
36 #define PHY_WRITE_LEVELING_DISB (0 << 2)
37 #define PHY_SELECT_CS0 (2)
38 #define PHY_SELECT_CS1 (1)
39 #define PHY_SELECT_CS0_1 (0)
40 #define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6)
41 #define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4)
55 void phy_soft_reset(void __iomem *phy_base);
56 void phy_dram_set_bw(void __iomem *phy_base, u32 bw);
57 void phy_cfg(void __iomem *phy_base,
58 struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew,
59 struct sdram_base_params *base, u32 bw);
60 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);