1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
6 #ifndef _ASM_ARCH_SDRAM_H
7 #define _ASM_ARCH_SDRAM_H
19 * sys_reg2 bitfield struct
26 * [23:22] low bits of cs0_row_ch1
27 * [21:20] low bits of cs1_row_ch1
35 * [7:6] low bits of cs0_row_ch0
36 * [5:4] low bits of cs1_row_ch0
40 #define SYS_REG_DDRTYPE_SHIFT 13
41 #define SYS_REG_DDRTYPE_MASK 7
42 #define SYS_REG_NUM_CH_SHIFT 12
43 #define SYS_REG_NUM_CH_MASK 1
44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
45 #define SYS_REG_ROW_3_4_MASK 1
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
48 #define SYS_REG_RANK_MASK 1
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
50 #define SYS_REG_COL_MASK 3
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
52 #define SYS_REG_BK_MASK 1
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
54 #define SYS_REG_CS0_ROW_MASK 3
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
56 #define SYS_REG_CS1_ROW_MASK 3
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
58 #define SYS_REG_BW_MASK 3
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
60 #define SYS_REG_DBW_MASK 3
63 * sys_reg3 bitfield struct
64 * [7] high bit of cs0_row_ch1
65 * [6] high bit of cs1_row_ch1
66 * [5] high bit of cs0_row_ch0
67 * [4] high bit of cs1_row_ch0
71 #define SYS_REG_VERSION_SHIFT 28
72 #define SYS_REG_VERSION_MASK 0xf
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2)
74 #define SYS_REG_EXTEND_CS0_ROW_MASK 1
75 #define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2)
76 #define SYS_REG_EXTEND_CS1_ROW_MASK 1
77 #define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2)
78 #define SYS_REG_CS1_COL_MASK 3
80 /* Get sdram size decode from reg */
81 size_t rockchip_sdram_size(phys_addr_t reg);
83 /* Called by U-Boot board_init_r for Rockchip SoCs */