1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
7 #ifndef __SOC_ROCKCHIP_RK3399_PMU_H__
8 #define __SOC_ROCKCHIP_RK3399_PMU_H__
10 struct rk3399_pmu_regs {
11 u32 pmu_wakeup_cfg[5];
19 u32 pmu_gpio0_pos_int_con;
20 u32 pmu_gpio0_net_int_con;
21 u32 pmu_gpio1_pos_int_con;
22 u32 pmu_gpio1_net_int_con;
23 u32 pmu_gpio0_pos_int_st;
24 u32 pmu_gpio0_net_int_st;
25 u32 pmu_gpio1_pos_int_st;
26 u32 pmu_gpio1_net_int_st;
29 u32 pmu_wakeup_status;
43 u32 pmu_ddrio_pwron_cnt;
44 u32 pmu_wakeup_rst_clr_cnt;
46 u32 pmu_scu_l_pwrdn_cnt;
47 u32 pmu_scu_l_pwrup_cnt;
48 u32 pmu_scu_b_pwrdn_cnt;
49 u32 pmu_scu_b_pwrup_cnt;
50 u32 pmu_gpu_pwrdn_cnt;
51 u32 pmu_gpu_pwrup_cnt;
52 u32 pmu_center_pwrdn_cnt;
53 u32 pmu_center_pwrup_cnt;
70 check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
72 #endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */