2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
8 #define __SOC_ROCKCHIP_RK3399_GRF_H__
10 struct rk3399_grf_regs {
15 u32 usb3_perf_rd_max_latency_num;
16 u32 usb3_perf_rd_latency_samp_num;
17 u32 usb3_perf_rd_latency_acc_num;
18 u32 usb3_perf_rd_axi_total_byte;
19 u32 usb3_perf_wr_axi_total_byte;
20 u32 usb3_perf_working_cnt;
28 u32 usb3otg0_status_lat0;
29 u32 usb3otg0_status_lat1;
30 u32 usb3otg0_status_cb;
32 u32 usb3otg1_status_lat0;
33 u32 usb3otg1_status_lat1;
34 u32 usb3ogt1_status_cb;
39 u32 pcie_perf_rd_max_latency_num;
40 u32 pcie_perf_rd_latency_samp_num;
41 u32 pcie_perf_rd_laterncy_acc_num;
42 u32 pcie_perf_rd_axi_total_byte;
43 u32 pcie_perf_wr_axi_total_byte;
44 u32 pcie_perf_working_cnt;
55 u32 grf_usbhost0_status;
56 u32 grf_usbhost1_Status;
64 u32 reserved13[0x72f];
74 u32 reserved15[0xf65];
80 u32 a53_perf_rd_mon_st;
81 u32 a53_perf_rd_mon_end;
82 u32 a53_perf_wr_mon_st;
83 u32 a53_perf_wr_mon_end;
84 u32 a53_perf_rd_max_latency_num;
85 u32 a53_perf_rd_latency_samp_num;
86 u32 a53_perf_rd_laterncy_acc_num;
87 u32 a53_perf_rd_axi_total_byte;
88 u32 a53_perf_wr_axi_total_byte;
89 u32 a53_perf_working_cnt;
90 u32 a53_perf_int_status;
93 u32 a72_perf_rd_mon_st;
94 u32 a72_perf_rd_mon_end;
95 u32 a72_perf_wr_mon_st;
96 u32 a72_perf_wr_mon_end;
97 u32 a72_perf_rd_max_latency_num;
98 u32 a72_perf_rd_latency_samp_num;
99 u32 a72_perf_rd_laterncy_acc_num;
100 u32 a72_perf_rd_axi_total_byte;
101 u32 a72_perf_wr_axi_total_byte;
102 u32 a72_perf_working_cnt;
103 u32 a72_perf_int_status;
104 u32 reserved19[0x7f6];
107 u32 reserved20[0x779];
142 u32 iomux_edp_hotplug;
152 u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
155 u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
166 u32 reserved26[0x1e];
168 u32 reserved27[0x32];
173 u32 reserved28[0xac];
178 u32 reserved29[0x6c];
180 u32 reserved30[0x1f];
182 u32 reserved31[0x1df];
183 u32 emmccore_con[12];
185 u32 emmccore_status[4];
186 u32 reserved33[0x1cc];
191 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
193 struct rk3399_pmugrf_regs {
254 u32 reserved17[0x24];
260 u32 reserved18[0x2b];
266 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
268 struct rk3399_pmusgrf_regs {
270 u32 reserved[0x1fe5];
288 u32 reserved5[0xfaf];
301 u32 reserved10[0x771];
311 u32 reserved12[0xdd];
319 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
322 /* GRF_GPIO2B_IOMUX */
323 GRF_GPIO2B1_SEL_SHIFT = 0,
324 GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
326 GRF_GPIO2B2_SEL_SHIFT = 2,
327 GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
329 GRF_GPIO2B3_SEL_SHIFT = 6,
330 GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
332 GRF_GPIO2B4_SEL_SHIFT = 8,
333 GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
334 GRF_SPI2TPM_CSN0 = 1,
336 /* GRF_GPIO3A_IOMUX */
337 GRF_GPIO3A4_SEL_SHIFT = 8,
338 GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
339 GRF_SPI0NORCODEC_RXD = 2,
340 GRF_GPIO3A5_SEL_SHIFT = 10,
341 GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
342 GRF_SPI0NORCODEC_TXD = 2,
343 GRF_GPIO3A6_SEL_SHIFT = 12,
344 GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
345 GRF_SPI0NORCODEC_CLK = 2,
346 GRF_GPIO3A7_SEL_SHIFT = 14,
347 GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
348 GRF_SPI0NORCODEC_CSN0 = 2,
350 /* GRF_GPIO3B_IOMUX */
351 GRF_GPIO3B0_SEL_SHIFT = 0,
352 GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
353 GRF_SPI0NORCODEC_CSN1 = 2,
355 /* GRF_GPIO4B_IOMUX */
356 GRF_GPIO4B0_SEL_SHIFT = 0,
357 GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT,
359 GRF_UART2DBGA_SIN = 2,
360 GRF_GPIO4B1_SEL_SHIFT = 2,
361 GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT,
363 GRF_UART2DBGA_SOUT = 2,
364 GRF_GPIO4B2_SEL_SHIFT = 4,
365 GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT,
367 GRF_GPIO4B3_SEL_SHIFT = 6,
368 GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT,
370 GRF_GPIO4B4_SEL_SHIFT = 8,
371 GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT,
372 GRF_SDMMC_CLKOUT = 1,
373 GRF_GPIO4B5_SEL_SHIFT = 10,
374 GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT,
377 /* GRF_GPIO4C_IOMUX */
378 GRF_GPIO4C0_SEL_SHIFT = 0,
379 GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
380 GRF_UART2DGBB_SIN = 2,
381 GRF_GPIO4C1_SEL_SHIFT = 2,
382 GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
383 GRF_UART2DGBB_SOUT = 2,
384 GRF_GPIO4C2_SEL_SHIFT = 4,
385 GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
387 GRF_GPIO4C3_SEL_SHIFT = 6,
388 GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
389 GRF_UART2DGBC_SIN = 1,
390 GRF_GPIO4C4_SEL_SHIFT = 8,
391 GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
392 GRF_UART2DBGC_SOUT = 1,
393 GRF_GPIO4C6_SEL_SHIFT = 12,
394 GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT,
398 GRF_UART_DBG_SEL_SHIFT = 10,
399 GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
400 GRF_UART_DBG_SEL_C = 2,
402 /* PMUGRF_GPIO0A_IOMUX */
403 PMUGRF_GPIO0A6_SEL_SHIFT = 12,
404 PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
407 /* PMUGRF_GPIO1A_IOMUX */
408 PMUGRF_GPIO1A7_SEL_SHIFT = 14,
409 PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
410 PMUGRF_SPI1EC_RXD = 2,
412 /* PMUGRF_GPIO1B_IOMUX */
413 PMUGRF_GPIO1B0_SEL_SHIFT = 0,
414 PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
415 PMUGRF_SPI1EC_TXD = 2,
416 PMUGRF_GPIO1B1_SEL_SHIFT = 2,
417 PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
418 PMUGRF_SPI1EC_CLK = 2,
419 PMUGRF_GPIO1B2_SEL_SHIFT = 4,
420 PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
421 PMUGRF_SPI1EC_CSN0 = 2,
422 PMUGRF_GPIO1B6_SEL_SHIFT = 12,
423 PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
425 PMUGRF_GPIO1B7_SEL_SHIFT = 14,
426 PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
427 PMUGRF_I2C0PMU_SDA = 2,
429 /* PMUGRF_GPIO1C_IOMUX */
430 PMUGRF_GPIO1C0_SEL_SHIFT = 0,
431 PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
432 PMUGRF_I2C0PMU_SCL = 2,
433 PMUGRF_GPIO1C3_SEL_SHIFT = 6,
434 PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
439 #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */