2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
8 #define __SOC_ROCKCHIP_RK3399_GRF_H__
10 struct rk3399_grf_regs {
15 u32 usb3_perf_rd_max_latency_num;
16 u32 usb3_perf_rd_latency_samp_num;
17 u32 usb3_perf_rd_latency_acc_num;
18 u32 usb3_perf_rd_axi_total_byte;
19 u32 usb3_perf_wr_axi_total_byte;
20 u32 usb3_perf_working_cnt;
28 u32 usb3otg0_status_lat0;
29 u32 usb3otg0_status_lat1;
30 u32 usb3otg0_status_cb;
32 u32 usb3otg1_status_lat0;
33 u32 usb3otg1_status_lat1;
34 u32 usb3ogt1_status_cb;
39 u32 pcie_perf_rd_max_latency_num;
40 u32 pcie_perf_rd_latency_samp_num;
41 u32 pcie_perf_rd_laterncy_acc_num;
42 u32 pcie_perf_rd_axi_total_byte;
43 u32 pcie_perf_wr_axi_total_byte;
44 u32 pcie_perf_working_cnt;
55 u32 grf_usbhost0_status;
56 u32 grf_usbhost1_Status;
64 u32 reserved13[0x72f];
74 u32 reserved15[0xf65];
80 u32 a53_perf_rd_mon_st;
81 u32 a53_perf_rd_mon_end;
82 u32 a53_perf_wr_mon_st;
83 u32 a53_perf_wr_mon_end;
84 u32 a53_perf_rd_max_latency_num;
85 u32 a53_perf_rd_latency_samp_num;
86 u32 a53_perf_rd_laterncy_acc_num;
87 u32 a53_perf_rd_axi_total_byte;
88 u32 a53_perf_wr_axi_total_byte;
89 u32 a53_perf_working_cnt;
90 u32 a53_perf_int_status;
93 u32 a72_perf_rd_mon_st;
94 u32 a72_perf_rd_mon_end;
95 u32 a72_perf_wr_mon_st;
96 u32 a72_perf_wr_mon_end;
97 u32 a72_perf_rd_max_latency_num;
98 u32 a72_perf_rd_latency_samp_num;
99 u32 a72_perf_rd_laterncy_acc_num;
100 u32 a72_perf_rd_axi_total_byte;
101 u32 a72_perf_wr_axi_total_byte;
102 u32 a72_perf_working_cnt;
103 u32 a72_perf_int_status;
104 u32 reserved19[0x7f6];
107 u32 reserved20[0x779];
142 u32 iomux_edp_hotplug;
154 u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
157 u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
168 u32 reserved26[0x1e];
170 u32 reserved27[0x32];
175 u32 reserved28[0xac];
180 u32 reserved29[0x6c];
182 u32 reserved30[0x1f];
184 u32 reserved31[0x1df];
185 u32 emmccore_con[12];
187 u32 emmccore_status[4];
188 u32 reserved33[0x1cc];
193 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
195 struct rk3399_pmugrf_regs {
258 u32 reserved17[0x24];
264 u32 reserved18[0x2b];
270 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
272 struct rk3399_pmusgrf_regs {
274 u32 reserved[0x1fe5];
292 u32 reserved5[0xfaf];
305 u32 reserved10[0x771];
315 u32 reserved12[0xdd];
323 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
326 /* GRF_GPIO2B_IOMUX */
327 GRF_GPIO2B1_SEL_SHIFT = 0,
328 GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
330 GRF_GPIO2B2_SEL_SHIFT = 2,
331 GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
333 GRF_GPIO2B3_SEL_SHIFT = 6,
334 GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
336 GRF_GPIO2B4_SEL_SHIFT = 8,
337 GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
338 GRF_SPI2TPM_CSN0 = 1,
340 /* GRF_GPIO2C_IOMUX */
341 GRF_GPIO2C0_SEL_SHIFT = 0,
342 GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT,
344 GRF_GPIO2C1_SEL_SHIFT = 2,
345 GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
346 GRF_UART0BT_SOUT = 1,
348 /* GRF_GPIO3A_IOMUX */
349 GRF_GPIO3A0_SEL_SHIFT = 0,
350 GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT,
352 GRF_GPIO3A1_SEL_SHIFT = 2,
353 GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT,
355 GRF_GPIO3A2_SEL_SHIFT = 4,
356 GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT,
358 GRF_GPIO3A3_SEL_SHIFT = 6,
359 GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT,
361 GRF_GPIO3A4_SEL_SHIFT = 8,
362 GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
364 GRF_SPI0NORCODEC_RXD = 2,
365 GRF_GPIO3A5_SEL_SHIFT = 10,
366 GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
368 GRF_SPI0NORCODEC_TXD = 2,
369 GRF_GPIO3A6_SEL_SHIFT = 12,
370 GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
372 GRF_SPI0NORCODEC_CLK = 2,
373 GRF_GPIO3A7_SEL_SHIFT = 14,
374 GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
376 GRF_SPI0NORCODEC_CSN0 = 2,
378 /* GRF_GPIO3B_IOMUX */
379 GRF_GPIO3B0_SEL_SHIFT = 0,
380 GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
382 GRF_SPI0NORCODEC_CSN1 = 2,
383 GRF_GPIO3B1_SEL_SHIFT = 2,
384 GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT,
386 GRF_GPIO3B3_SEL_SHIFT = 6,
387 GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT,
389 GRF_GPIO3B4_SEL_SHIFT = 8,
390 GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT,
392 GRF_GPIO3B5_SEL_SHIFT = 10,
393 GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT,
395 GRF_GPIO3B6_SEL_SHIFT = 12,
396 GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT,
399 /* GRF_GPIO3C_IOMUX */
400 GRF_GPIO3C1_SEL_SHIFT = 2,
401 GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT,
404 /* GRF_GPIO4B_IOMUX */
405 GRF_GPIO4B0_SEL_SHIFT = 0,
406 GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT,
408 GRF_UART2DBGA_SIN = 2,
409 GRF_GPIO4B1_SEL_SHIFT = 2,
410 GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT,
412 GRF_UART2DBGA_SOUT = 2,
413 GRF_GPIO4B2_SEL_SHIFT = 4,
414 GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT,
416 GRF_GPIO4B3_SEL_SHIFT = 6,
417 GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT,
419 GRF_GPIO4B4_SEL_SHIFT = 8,
420 GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT,
421 GRF_SDMMC_CLKOUT = 1,
422 GRF_GPIO4B5_SEL_SHIFT = 10,
423 GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT,
426 /* GRF_GPIO4C_IOMUX */
427 GRF_GPIO4C0_SEL_SHIFT = 0,
428 GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
429 GRF_UART2DGBB_SIN = 2,
430 GRF_GPIO4C1_SEL_SHIFT = 2,
431 GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
432 GRF_UART2DGBB_SOUT = 2,
433 GRF_GPIO4C2_SEL_SHIFT = 4,
434 GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
436 GRF_GPIO4C3_SEL_SHIFT = 6,
437 GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
438 GRF_UART2DGBC_SIN = 1,
439 GRF_GPIO4C4_SEL_SHIFT = 8,
440 GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
441 GRF_UART2DBGC_SOUT = 1,
442 GRF_GPIO4C6_SEL_SHIFT = 12,
443 GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT,
447 GRF_UART_DBG_SEL_SHIFT = 10,
448 GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
449 GRF_UART_DBG_SEL_C = 2,
451 /* PMUGRF_GPIO0A_IOMUX */
452 PMUGRF_GPIO0A6_SEL_SHIFT = 12,
453 PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
456 /* PMUGRF_GPIO1A_IOMUX */
457 PMUGRF_GPIO1A7_SEL_SHIFT = 14,
458 PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
459 PMUGRF_SPI1EC_RXD = 2,
461 /* PMUGRF_GPIO1B_IOMUX */
462 PMUGRF_GPIO1B0_SEL_SHIFT = 0,
463 PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
464 PMUGRF_SPI1EC_TXD = 2,
465 PMUGRF_GPIO1B1_SEL_SHIFT = 2,
466 PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
467 PMUGRF_SPI1EC_CLK = 2,
468 PMUGRF_GPIO1B2_SEL_SHIFT = 4,
469 PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
470 PMUGRF_SPI1EC_CSN0 = 2,
471 PMUGRF_GPIO1B6_SEL_SHIFT = 12,
472 PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
474 PMUGRF_GPIO1B7_SEL_SHIFT = 14,
475 PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
476 PMUGRF_I2C0PMU_SDA = 2,
478 /* PMUGRF_GPIO1C_IOMUX */
479 PMUGRF_GPIO1C0_SEL_SHIFT = 0,
480 PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
481 PMUGRF_I2C0PMU_SCL = 2,
482 PMUGRF_GPIO1C3_SEL_SHIFT = 6,
483 PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
490 RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
491 RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
492 RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
493 RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
495 RK3399_GMAC_CLK_SEL_SHIFT = 4,
496 RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
497 RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
498 RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
499 RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
504 RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
505 RK3399_RXCLK_DLY_ENA_GMAC_MASK =
506 (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
507 RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
508 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
509 (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
511 RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7,
512 RK3399_TXCLK_DLY_ENA_GMAC_MASK =
513 (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
514 RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
515 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
516 (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
518 RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
519 RK3399_CLK_RX_DL_CFG_GMAC_MASK =
520 (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
522 RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
523 RK3399_CLK_TX_DL_CFG_GMAC_MASK =
524 (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
527 #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */