2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
8 #define __SOC_ROCKCHIP_RK3399_GRF_H__
10 struct rk3399_grf_regs {
15 u32 usb3_perf_rd_max_latency_num;
16 u32 usb3_perf_rd_latency_samp_num;
17 u32 usb3_perf_rd_latency_acc_num;
18 u32 usb3_perf_rd_axi_total_byte;
19 u32 usb3_perf_wr_axi_total_byte;
20 u32 usb3_perf_working_cnt;
28 u32 usb3otg0_status_lat0;
29 u32 usb3otg0_status_lat1;
30 u32 usb3otg0_status_cb;
32 u32 usb3otg1_status_lat0;
33 u32 usb3otg1_status_lat1;
34 u32 usb3ogt1_status_cb;
39 u32 pcie_perf_rd_max_latency_num;
40 u32 pcie_perf_rd_latency_samp_num;
41 u32 pcie_perf_rd_laterncy_acc_num;
42 u32 pcie_perf_rd_axi_total_byte;
43 u32 pcie_perf_wr_axi_total_byte;
44 u32 pcie_perf_working_cnt;
55 u32 grf_usbhost0_status;
56 u32 grf_usbhost1_Status;
64 u32 reserved13[0x72f];
74 u32 reserved15[0xf65];
80 u32 a53_perf_rd_mon_st;
81 u32 a53_perf_rd_mon_end;
82 u32 a53_perf_wr_mon_st;
83 u32 a53_perf_wr_mon_end;
84 u32 a53_perf_rd_max_latency_num;
85 u32 a53_perf_rd_latency_samp_num;
86 u32 a53_perf_rd_laterncy_acc_num;
87 u32 a53_perf_rd_axi_total_byte;
88 u32 a53_perf_wr_axi_total_byte;
89 u32 a53_perf_working_cnt;
90 u32 a53_perf_int_status;
93 u32 a72_perf_rd_mon_st;
94 u32 a72_perf_rd_mon_end;
95 u32 a72_perf_wr_mon_st;
96 u32 a72_perf_wr_mon_end;
97 u32 a72_perf_rd_max_latency_num;
98 u32 a72_perf_rd_latency_samp_num;
99 u32 a72_perf_rd_laterncy_acc_num;
100 u32 a72_perf_rd_axi_total_byte;
101 u32 a72_perf_wr_axi_total_byte;
102 u32 a72_perf_working_cnt;
103 u32 a72_perf_int_status;
104 u32 reserved19[0x7f6];
107 u32 reserved20[0x779];
142 u32 iomux_edp_hotplug;
154 u32 reserved24[(0xe100 - 0xe0ec)/4 - 1];
158 u32 reserved24a[(0xe200 - 0xe13c)/4 - 1];
169 u32 reserved26[0x1e];
171 u32 reserved27[0x32];
176 u32 reserved28[0xac];
181 u32 reserved29[0x6c];
183 u32 reserved30[0x1f];
185 u32 reserved31[0x1df];
186 u32 emmccore_con[12];
188 u32 emmccore_status[4];
189 u32 reserved33[0x1cc];
194 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
196 struct rk3399_pmugrf_regs {
259 u32 reserved17[0x24];
265 u32 reserved18[0x2b];
271 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
273 struct rk3399_pmusgrf_regs {
275 u32 reserved[0x1fe5];
293 u32 reserved5[0xfaf];
306 u32 reserved10[0x771];
316 u32 reserved12[0xdd];
324 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
327 /* GRF_GPIO2B_IOMUX */
328 GRF_GPIO2B1_SEL_SHIFT = 0,
329 GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
331 GRF_GPIO2B2_SEL_SHIFT = 2,
332 GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
334 GRF_GPIO2B3_SEL_SHIFT = 6,
335 GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
337 GRF_GPIO2B4_SEL_SHIFT = 8,
338 GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
339 GRF_SPI2TPM_CSN0 = 1,
341 /* GRF_GPIO2C_IOMUX */
342 GRF_GPIO2C0_SEL_SHIFT = 0,
343 GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT,
345 GRF_GPIO2C1_SEL_SHIFT = 2,
346 GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
347 GRF_UART0BT_SOUT = 1,
348 GRF_GPIO2C4_SEL_SHIFT = 8,
349 GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT,
350 GRF_SPI5EXPPLUS_RXD = 2,
351 GRF_GPIO2C5_SEL_SHIFT = 10,
352 GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT,
353 GRF_SPI5EXPPLUS_TXD = 2,
354 GRF_GPIO2C6_SEL_SHIFT = 12,
355 GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT,
356 GRF_SPI5EXPPLUS_CLK = 2,
357 GRF_GPIO2C7_SEL_SHIFT = 14,
358 GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT,
359 GRF_SPI5EXPPLUS_CSN0 = 2,
361 /* GRF_GPIO3A_IOMUX */
362 GRF_GPIO3A0_SEL_SHIFT = 0,
363 GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT,
365 GRF_GPIO3A1_SEL_SHIFT = 2,
366 GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT,
368 GRF_GPIO3A2_SEL_SHIFT = 4,
369 GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT,
371 GRF_GPIO3A3_SEL_SHIFT = 6,
372 GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT,
374 GRF_GPIO3A4_SEL_SHIFT = 8,
375 GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
377 GRF_SPI0NORCODEC_RXD = 2,
378 GRF_GPIO3A5_SEL_SHIFT = 10,
379 GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
381 GRF_SPI0NORCODEC_TXD = 2,
382 GRF_GPIO3A6_SEL_SHIFT = 12,
383 GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
385 GRF_SPI0NORCODEC_CLK = 2,
386 GRF_GPIO3A7_SEL_SHIFT = 14,
387 GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
389 GRF_SPI0NORCODEC_CSN0 = 2,
391 /* GRF_GPIO3B_IOMUX */
392 GRF_GPIO3B0_SEL_SHIFT = 0,
393 GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
395 GRF_SPI0NORCODEC_CSN1 = 2,
396 GRF_GPIO3B1_SEL_SHIFT = 2,
397 GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT,
399 GRF_GPIO3B3_SEL_SHIFT = 6,
400 GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT,
402 GRF_GPIO3B4_SEL_SHIFT = 8,
403 GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT,
405 GRF_GPIO3B5_SEL_SHIFT = 10,
406 GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT,
408 GRF_GPIO3B6_SEL_SHIFT = 12,
409 GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT,
412 /* GRF_GPIO3C_IOMUX */
413 GRF_GPIO3C1_SEL_SHIFT = 2,
414 GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT,
417 /* GRF_GPIO4B_IOMUX */
418 GRF_GPIO4B0_SEL_SHIFT = 0,
419 GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT,
421 GRF_UART2DBGA_SIN = 2,
422 GRF_GPIO4B1_SEL_SHIFT = 2,
423 GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT,
425 GRF_UART2DBGA_SOUT = 2,
426 GRF_GPIO4B2_SEL_SHIFT = 4,
427 GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT,
429 GRF_GPIO4B3_SEL_SHIFT = 6,
430 GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT,
432 GRF_GPIO4B4_SEL_SHIFT = 8,
433 GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT,
434 GRF_SDMMC_CLKOUT = 1,
435 GRF_GPIO4B5_SEL_SHIFT = 10,
436 GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT,
439 /* GRF_GPIO4C_IOMUX */
440 GRF_GPIO4C0_SEL_SHIFT = 0,
441 GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
442 GRF_UART2DGBB_SIN = 2,
444 GRF_GPIO4C1_SEL_SHIFT = 2,
445 GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
446 GRF_UART2DGBB_SOUT = 2,
448 GRF_GPIO4C2_SEL_SHIFT = 4,
449 GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
451 GRF_GPIO4C3_SEL_SHIFT = 6,
452 GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
453 GRF_UART2DGBC_SIN = 1,
454 GRF_GPIO4C4_SEL_SHIFT = 8,
455 GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
456 GRF_UART2DBGC_SOUT = 1,
457 GRF_GPIO4C6_SEL_SHIFT = 12,
458 GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT,
462 GRF_GPIO3A0_E_SHIFT = 0,
463 GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT,
464 GRF_GPIO3A1_E_SHIFT = 3,
465 GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT,
466 GRF_GPIO3A2_E_SHIFT = 6,
467 GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT,
468 GRF_GPIO3A3_E_SHIFT = 9,
469 GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT,
470 GRF_GPIO3A4_E_SHIFT = 12,
471 GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT,
472 GRF_GPIO3A5_E0_SHIFT = 15,
473 GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT,
476 GRF_GPIO3A5_E12_SHIFT = 0,
477 GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT,
478 GRF_GPIO3A6_E_SHIFT = 2,
479 GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT,
480 GRF_GPIO3A7_E_SHIFT = 5,
481 GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT,
484 GRF_GPIO3B0_E_SHIFT = 0,
485 GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT,
486 GRF_GPIO3B1_E_SHIFT = 3,
487 GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT,
488 GRF_GPIO3B2_E_SHIFT = 6,
489 GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT,
490 GRF_GPIO3B3_E_SHIFT = 9,
491 GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT,
492 GRF_GPIO3B4_E_SHIFT = 12,
493 GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT,
494 GRF_GPIO3B5_E0_SHIFT = 15,
495 GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT,
498 GRF_GPIO3B5_E12_SHIFT = 0,
499 GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT,
500 GRF_GPIO3B6_E_SHIFT = 2,
501 GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT,
502 GRF_GPIO3B7_E_SHIFT = 5,
503 GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT,
506 GRF_GPIO3C0_E_SHIFT = 0,
507 GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT,
508 GRF_GPIO3C1_E_SHIFT = 3,
509 GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT,
510 GRF_GPIO3C2_E_SHIFT = 6,
511 GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT,
512 GRF_GPIO3C3_E_SHIFT = 9,
513 GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT,
514 GRF_GPIO3C4_E_SHIFT = 12,
515 GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT,
516 GRF_GPIO3C5_E0_SHIFT = 15,
517 GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT,
520 GRF_GPIO3C5_E12_SHIFT = 0,
521 GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT,
522 GRF_GPIO3C6_E_SHIFT = 2,
523 GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT,
524 GRF_GPIO3C7_E_SHIFT = 5,
525 GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT,
528 GRF_UART_DBG_SEL_SHIFT = 10,
529 GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
530 GRF_UART_DBG_SEL_C = 2,
533 GRF_DSI0_VOP_SEL_SHIFT = 0,
534 GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT,
535 GRF_DSI0_VOP_SEL_B = 0,
536 GRF_DSI0_VOP_SEL_L = 1,
539 GRF_DPHY_TX0_RXMODE_SHIFT = 0,
540 GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
541 GRF_DPHY_TX0_RXMODE_EN = 0xb,
542 GRF_DPHY_TX0_RXMODE_DIS = 0,
544 GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
545 GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
546 GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,
547 GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,
549 GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
550 GRF_DPHY_TX0_TURNREQUEST_MASK =
551 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
552 GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,
553 GRF_DPHY_TX0_TURNREQUEST_DIS = 0,
555 /* PMUGRF_GPIO0A_IOMUX */
556 PMUGRF_GPIO0A6_SEL_SHIFT = 12,
557 PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
560 /* PMUGRF_GPIO1A_IOMUX */
561 PMUGRF_GPIO1A7_SEL_SHIFT = 14,
562 PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
563 PMUGRF_SPI1EC_RXD = 2,
565 /* PMUGRF_GPIO1B_IOMUX */
566 PMUGRF_GPIO1B0_SEL_SHIFT = 0,
567 PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
568 PMUGRF_SPI1EC_TXD = 2,
569 PMUGRF_GPIO1B1_SEL_SHIFT = 2,
570 PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
571 PMUGRF_SPI1EC_CLK = 2,
572 PMUGRF_GPIO1B2_SEL_SHIFT = 4,
573 PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
574 PMUGRF_SPI1EC_CSN0 = 2,
575 PMUGRF_GPIO1B6_SEL_SHIFT = 12,
576 PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
578 PMUGRF_GPIO1B7_SEL_SHIFT = 14,
579 PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
580 PMUGRF_I2C0PMU_SDA = 2,
582 /* PMUGRF_GPIO1C_IOMUX */
583 PMUGRF_GPIO1C0_SEL_SHIFT = 0,
584 PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
585 PMUGRF_I2C0PMU_SCL = 2,
586 PMUGRF_GPIO1C3_SEL_SHIFT = 6,
587 PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
594 RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
595 RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
596 RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
597 RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
599 RK3399_GMAC_CLK_SEL_SHIFT = 4,
600 RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
601 RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
602 RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
603 RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
608 RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
609 RK3399_RXCLK_DLY_ENA_GMAC_MASK =
610 (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
611 RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
612 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
613 (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
615 RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7,
616 RK3399_TXCLK_DLY_ENA_GMAC_MASK =
617 (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
618 RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
619 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
620 (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
622 RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
623 RK3399_CLK_RX_DL_CFG_GMAC_MASK =
624 (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
626 RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
627 RK3399_CLK_TX_DL_CFG_GMAC_MASK =
628 (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
631 #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */