1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
6 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
7 #define __SOC_ROCKCHIP_RK3399_GRF_H__
9 struct rk3399_grf_regs {
14 u32 usb3_perf_rd_max_latency_num;
15 u32 usb3_perf_rd_latency_samp_num;
16 u32 usb3_perf_rd_latency_acc_num;
17 u32 usb3_perf_rd_axi_total_byte;
18 u32 usb3_perf_wr_axi_total_byte;
19 u32 usb3_perf_working_cnt;
27 u32 usb3otg0_status_lat0;
28 u32 usb3otg0_status_lat1;
29 u32 usb3otg0_status_cb;
31 u32 usb3otg1_status_lat0;
32 u32 usb3otg1_status_lat1;
33 u32 usb3ogt1_status_cb;
38 u32 pcie_perf_rd_max_latency_num;
39 u32 pcie_perf_rd_latency_samp_num;
40 u32 pcie_perf_rd_laterncy_acc_num;
41 u32 pcie_perf_rd_axi_total_byte;
42 u32 pcie_perf_wr_axi_total_byte;
43 u32 pcie_perf_working_cnt;
54 u32 grf_usbhost0_status;
55 u32 grf_usbhost1_Status;
63 u32 reserved13[0x72f];
73 u32 reserved15[0xf65];
79 u32 a53_perf_rd_mon_st;
80 u32 a53_perf_rd_mon_end;
81 u32 a53_perf_wr_mon_st;
82 u32 a53_perf_wr_mon_end;
83 u32 a53_perf_rd_max_latency_num;
84 u32 a53_perf_rd_latency_samp_num;
85 u32 a53_perf_rd_laterncy_acc_num;
86 u32 a53_perf_rd_axi_total_byte;
87 u32 a53_perf_wr_axi_total_byte;
88 u32 a53_perf_working_cnt;
89 u32 a53_perf_int_status;
92 u32 a72_perf_rd_mon_st;
93 u32 a72_perf_rd_mon_end;
94 u32 a72_perf_wr_mon_st;
95 u32 a72_perf_wr_mon_end;
96 u32 a72_perf_rd_max_latency_num;
97 u32 a72_perf_rd_latency_samp_num;
98 u32 a72_perf_rd_laterncy_acc_num;
99 u32 a72_perf_rd_axi_total_byte;
100 u32 a72_perf_wr_axi_total_byte;
101 u32 a72_perf_working_cnt;
102 u32 a72_perf_int_status;
103 u32 reserved19[0x7f6];
106 u32 reserved20[0x779];
141 u32 iomux_edp_hotplug;
153 u32 reserved24[(0xe100 - 0xe0ec)/4 - 1];
157 u32 reserved24a[(0xe200 - 0xe13c)/4 - 1];
168 u32 reserved26[0x1e];
170 u32 reserved27[0x32];
175 u32 reserved28[0xac];
180 u32 reserved29[0x6c];
182 u32 reserved30[0x1f];
184 u32 reserved31[0x1df];
185 u32 emmccore_con[12];
187 u32 emmccore_status[4];
188 u32 reserved33[0x1cc];
193 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
195 struct rk3399_pmugrf_regs {
258 u32 reserved17[0x24];
264 u32 reserved18[0x2b];
270 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
272 struct rk3399_pmusgrf_regs {
274 u32 reserved[0x1fe5];
292 u32 reserved5[0xfaf];
305 u32 reserved10[0x771];
315 u32 reserved12[0xdd];
323 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
326 /* GRF_GPIO2A_IOMUX */
327 GRF_GPIO2A0_SEL_SHIFT = 0,
328 GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT,
330 GRF_GPIO2A1_SEL_SHIFT = 2,
331 GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT,
333 GRF_GPIO2A7_SEL_SHIFT = 14,
334 GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT,
337 /* GRF_GPIO2B_IOMUX */
338 GRF_GPIO2B0_SEL_SHIFT = 0,
339 GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT,
341 GRF_GPIO2B1_SEL_SHIFT = 2,
342 GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
345 GRF_GPIO2B2_SEL_SHIFT = 4,
346 GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
349 GRF_GPIO2B3_SEL_SHIFT = 6,
350 GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
352 GRF_GPIO2B4_SEL_SHIFT = 8,
353 GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
354 GRF_SPI2TPM_CSN0 = 1,
356 /* GRF_GPIO2C_IOMUX */
357 GRF_GPIO2C0_SEL_SHIFT = 0,
358 GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT,
360 GRF_GPIO2C1_SEL_SHIFT = 2,
361 GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
362 GRF_UART0BT_SOUT = 1,
363 GRF_GPIO2C4_SEL_SHIFT = 8,
364 GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT,
365 GRF_SPI5EXPPLUS_RXD = 2,
366 GRF_GPIO2C5_SEL_SHIFT = 10,
367 GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT,
368 GRF_SPI5EXPPLUS_TXD = 2,
369 GRF_GPIO2C6_SEL_SHIFT = 12,
370 GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT,
371 GRF_SPI5EXPPLUS_CLK = 2,
372 GRF_GPIO2C7_SEL_SHIFT = 14,
373 GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT,
374 GRF_SPI5EXPPLUS_CSN0 = 2,
376 /* GRF_GPIO3A_IOMUX */
377 GRF_GPIO3A0_SEL_SHIFT = 0,
378 GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT,
380 GRF_GPIO3A1_SEL_SHIFT = 2,
381 GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT,
383 GRF_GPIO3A2_SEL_SHIFT = 4,
384 GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT,
386 GRF_GPIO3A3_SEL_SHIFT = 6,
387 GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT,
389 GRF_GPIO3A4_SEL_SHIFT = 8,
390 GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
392 GRF_SPI0NORCODEC_RXD = 2,
393 GRF_GPIO3A5_SEL_SHIFT = 10,
394 GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
396 GRF_SPI0NORCODEC_TXD = 2,
397 GRF_GPIO3A6_SEL_SHIFT = 12,
398 GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
400 GRF_SPI0NORCODEC_CLK = 2,
401 GRF_GPIO3A7_SEL_SHIFT = 14,
402 GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
404 GRF_SPI0NORCODEC_CSN0 = 2,
406 /* GRF_GPIO3B_IOMUX */
407 GRF_GPIO3B0_SEL_SHIFT = 0,
408 GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
410 GRF_SPI0NORCODEC_CSN1 = 2,
411 GRF_GPIO3B1_SEL_SHIFT = 2,
412 GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT,
414 GRF_GPIO3B3_SEL_SHIFT = 6,
415 GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT,
417 GRF_GPIO3B4_SEL_SHIFT = 8,
418 GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT,
420 GRF_GPIO3B5_SEL_SHIFT = 10,
421 GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT,
423 GRF_GPIO3B6_SEL_SHIFT = 12,
424 GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT,
427 GRF_GPIO3B7_SEL_SHIFT = 14,
428 GRF_GPIO3B7_SEL_MASK = 3 << GRF_GPIO3B7_SEL_SHIFT,
431 /* GRF_GPIO3C_IOMUX */
432 GRF_GPIO3C1_SEL_SHIFT = 2,
433 GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT,
436 /* GRF_GPIO4A_IOMUX */
437 GRF_GPIO4A1_SEL_SHIFT = 2,
438 GRF_GPIO4A1_SEL_MASK = 3 << GRF_GPIO4A1_SEL_SHIFT,
440 GRF_GPIO4A2_SEL_SHIFT = 4,
441 GRF_GPIO4A2_SEL_MASK = 3 << GRF_GPIO4A2_SEL_SHIFT,
444 /* GRF_GPIO4B_IOMUX */
445 GRF_GPIO4B0_SEL_SHIFT = 0,
446 GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT,
448 GRF_UART2DBGA_SIN = 2,
449 GRF_GPIO4B1_SEL_SHIFT = 2,
450 GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT,
452 GRF_UART2DBGA_SOUT = 2,
453 GRF_GPIO4B2_SEL_SHIFT = 4,
454 GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT,
456 GRF_GPIO4B3_SEL_SHIFT = 6,
457 GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT,
459 GRF_GPIO4B4_SEL_SHIFT = 8,
460 GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT,
461 GRF_SDMMC_CLKOUT = 1,
462 GRF_GPIO4B5_SEL_SHIFT = 10,
463 GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT,
466 /* GRF_GPIO4C_IOMUX */
467 GRF_GPIO4C0_SEL_SHIFT = 0,
468 GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
469 GRF_UART2DGBB_SIN = 2,
471 GRF_GPIO4C1_SEL_SHIFT = 2,
472 GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
473 GRF_UART2DGBB_SOUT = 2,
475 GRF_GPIO4C2_SEL_SHIFT = 4,
476 GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
478 GRF_GPIO4C3_SEL_SHIFT = 6,
479 GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
480 GRF_UART2DGBC_SIN = 1,
481 GRF_GPIO4C4_SEL_SHIFT = 8,
482 GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
483 GRF_UART2DBGC_SOUT = 1,
484 GRF_GPIO4C6_SEL_SHIFT = 12,
485 GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT,
489 GRF_GPIO3A0_E_SHIFT = 0,
490 GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT,
491 GRF_GPIO3A1_E_SHIFT = 3,
492 GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT,
493 GRF_GPIO3A2_E_SHIFT = 6,
494 GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT,
495 GRF_GPIO3A3_E_SHIFT = 9,
496 GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT,
497 GRF_GPIO3A4_E_SHIFT = 12,
498 GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT,
499 GRF_GPIO3A5_E0_SHIFT = 15,
500 GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT,
503 GRF_GPIO3A5_E12_SHIFT = 0,
504 GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT,
505 GRF_GPIO3A6_E_SHIFT = 2,
506 GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT,
507 GRF_GPIO3A7_E_SHIFT = 5,
508 GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT,
511 GRF_GPIO3B0_E_SHIFT = 0,
512 GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT,
513 GRF_GPIO3B1_E_SHIFT = 3,
514 GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT,
515 GRF_GPIO3B2_E_SHIFT = 6,
516 GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT,
517 GRF_GPIO3B3_E_SHIFT = 9,
518 GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT,
519 GRF_GPIO3B4_E_SHIFT = 12,
520 GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT,
521 GRF_GPIO3B5_E0_SHIFT = 15,
522 GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT,
525 GRF_GPIO3B5_E12_SHIFT = 0,
526 GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT,
527 GRF_GPIO3B6_E_SHIFT = 2,
528 GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT,
529 GRF_GPIO3B7_E_SHIFT = 5,
530 GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT,
533 GRF_GPIO3C0_E_SHIFT = 0,
534 GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT,
535 GRF_GPIO3C1_E_SHIFT = 3,
536 GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT,
537 GRF_GPIO3C2_E_SHIFT = 6,
538 GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT,
539 GRF_GPIO3C3_E_SHIFT = 9,
540 GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT,
541 GRF_GPIO3C4_E_SHIFT = 12,
542 GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT,
543 GRF_GPIO3C5_E0_SHIFT = 15,
544 GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT,
547 GRF_GPIO3C5_E12_SHIFT = 0,
548 GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT,
549 GRF_GPIO3C6_E_SHIFT = 2,
550 GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT,
551 GRF_GPIO3C7_E_SHIFT = 5,
552 GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT,
555 GRF_UART_DBG_SEL_SHIFT = 10,
556 GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
557 GRF_UART_DBG_SEL_C = 2,
560 GRF_DSI0_VOP_SEL_SHIFT = 0,
561 GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT,
562 GRF_DSI0_VOP_SEL_B = 0,
563 GRF_DSI0_VOP_SEL_L = 1,
564 GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6,
565 GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6,
566 GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6,
569 GRF_DPHY_TX0_RXMODE_SHIFT = 0,
570 GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
571 GRF_DPHY_TX0_RXMODE_EN = 0xb,
572 GRF_DPHY_TX0_RXMODE_DIS = 0,
574 GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
575 GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
576 GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,
577 GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,
579 GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
580 GRF_DPHY_TX0_TURNREQUEST_MASK =
581 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
582 GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,
583 GRF_DPHY_TX0_TURNREQUEST_DIS = 0,
585 /* PMUGRF_GPIO0A_IOMUX */
586 PMUGRF_GPIO0A6_SEL_SHIFT = 12,
587 PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
590 /* PMUGRF_GPIO1A_IOMUX */
591 PMUGRF_GPIO1A7_SEL_SHIFT = 14,
592 PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
593 PMUGRF_SPI1EC_RXD = 2,
595 /* PMUGRF_GPIO1B_IOMUX */
596 PMUGRF_GPIO1B0_SEL_SHIFT = 0,
597 PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
598 PMUGRF_SPI1EC_TXD = 2,
599 PMUGRF_GPIO1B1_SEL_SHIFT = 2,
600 PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
601 PMUGRF_SPI1EC_CLK = 2,
602 PMUGRF_GPIO1B2_SEL_SHIFT = 4,
603 PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
604 PMUGRF_SPI1EC_CSN0 = 2,
605 PMUGRF_GPIO1B3_SEL_SHIFT = 6,
606 PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT,
608 PMUGRF_GPIO1B4_SEL_SHIFT = 8,
609 PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT,
611 PMUGRF_GPIO1B6_SEL_SHIFT = 12,
612 PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
614 PMUGRF_GPIO1B7_SEL_SHIFT = 14,
615 PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
616 PMUGRF_I2C0PMU_SDA = 2,
618 /* PMUGRF_GPIO1C_IOMUX */
619 PMUGRF_GPIO1C0_SEL_SHIFT = 0,
620 PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
621 PMUGRF_I2C0PMU_SCL = 2,
622 PMUGRF_GPIO1C3_SEL_SHIFT = 6,
623 PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
625 PMUGRF_GPIO1C4_SEL_SHIFT = 8,
626 PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT,
627 PMUGRF_I2C8PMU_SDA = 1,
628 PMUGRF_GPIO1C5_SEL_SHIFT = 10,
629 PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT,
630 PMUGRF_I2C8PMU_SCL = 1,
635 RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
636 RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
637 RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
638 RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
640 RK3399_GMAC_CLK_SEL_SHIFT = 4,
641 RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
642 RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
643 RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
644 RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
649 RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
650 RK3399_RXCLK_DLY_ENA_GMAC_MASK =
651 (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
652 RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
653 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
654 (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
656 RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7,
657 RK3399_TXCLK_DLY_ENA_GMAC_MASK =
658 (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
659 RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
660 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
661 (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
663 RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
664 RK3399_CLK_RX_DL_CFG_GMAC_MASK =
665 (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
667 RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
668 RK3399_CLK_TX_DL_CFG_GMAC_MASK =
669 (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
672 #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */