arch/arm/include/asm/arch-rockchip/grf_rk3368.h

   1 /* (C) Copyright 2016 Rockchip Electronics Co., Ltd
   2  *
   3  * SPDX-License-Identifier:     GPL-2.0+
   4  */
   5 #ifndef _ASM_ARCH_GRF_RK3368_H
   6 #define _ASM_ARCH_GRF_RK3368_H
   7
   8 #include <common.h>
   9
  10 struct rk3368_grf {
  11         u32 gpio1a_iomux;
  12         u32 gpio1b_iomux;
  13         u32 gpio1c_iomux;
  14         u32 gpio1d_iomux;
  15         u32 gpio2a_iomux;
  16         u32 gpio2b_iomux;
  17         u32 gpio2c_iomux;
  18         u32 gpio2d_iomux;
  19         u32 gpio3a_iomux;
  20         u32 gpio3b_iomux;
  21         u32 gpio3c_iomux;
  22         u32 gpio3d_iomux;
  23         u32 reserved[0x34];
  24         u32 gpio1a_pull;
  25         u32 gpio1b_pull;
  26         u32 gpio1c_pull;
  27         u32 gpio1d_pull;
  28         u32 gpio2a_pull;
  29         u32 gpio2b_pull;
  30         u32 gpio2c_pull;
  31         u32 gpio2d_pull;
  32         u32 gpio3a_pull;
  33         u32 gpio3b_pull;
  34         u32 gpio3c_pull;
  35         u32 gpio3d_pull;
  36         u32 reserved1[0x34];
  37         u32 gpio1a_drv;
  38         u32 gpio1b_drv;
  39         u32 gpio1c_drv;
  40         u32 gpio1d_drv;
  41         u32 gpio2a_drv;
  42         u32 gpio2b_drv;
  43         u32 gpio2c_drv;
  44         u32 gpio2d_drv;
  45         u32 gpio3a_drv;
  46         u32 gpio3b_drv;
  47         u32 gpio3c_drv;
  48         u32 gpio3d_drv;
  49         u32 reserved2[0x34];
  50         u32 gpio1l_sr;
  51         u32 gpio1h_sr;
  52         u32 gpio2l_sr;
  53         u32 gpio2h_sr;
  54         u32 gpio3l_sr;
  55         u32 gpio3h_sr;
  56         u32 reserved3[0x1a];
  57         u32 gpio_smt;
  58         u32 reserved4[0x1f];
  59         u32 soc_con0;
  60         u32 soc_con1;
  61         u32 soc_con2;
  62         u32 soc_con3;
  63         u32 soc_con4;
  64         u32 soc_con5;
  65         u32 soc_con6;
  66         u32 soc_con7;
  67         u32 soc_con8;
  68         u32 soc_con9;
  69         u32 soc_con10;
  70         u32 soc_con11;
  71         u32 soc_con12;
  72         u32 soc_con13;
  73         u32 soc_con14;
  74         u32 soc_con15;
  75         u32 soc_con16;
  76         u32 soc_con17;
  77 };
  78 check_member(rk3368_grf, soc_con17, 0x444);
  79
  80 struct rk3368_pmu_grf {
  81         u32 gpio0a_iomux;
  82         u32 gpio0b_iomux;
  83         u32 gpio0c_iomux;
  84         u32 gpio0d_iomux;
  85         u32 gpio0a_pull;
  86         u32 gpio0b_pull;
  87         u32 gpio0c_pull;
  88         u32 gpio0d_pull;
  89         u32 gpio0a_drv;
  90         u32 gpio0b_drv;
  91         u32 gpio0c_drv;
  92         u32 gpio0d_drv;
  93         u32 gpio0l_sr;
  94         u32 gpio0h_sr;
  95         u32 reserved[(0x200 - 0x34) / 4 - 1];
  96         u32 os_reg[4];
  97 };
  98 check_member(rk3368_pmu_grf, os_reg[3], 0x20c);
  99
 100 /*GRF_GPIO0C_IOMUX*/
 101 enum {
 102         GPIO0C7_SHIFT           = 14,
 103         GPIO0C7_MASK            = 3 << GPIO0C7_SHIFT,
 104         GPIO0C7_GPIO            = 0,
 105         GPIO0C7_LCDC_D19,
 106         GPIO0C7_TRACE_D9,
 107         GPIO0C7_UART1_RTSN,
 108
 109         GPIO0C6_SHIFT           = 12,
 110         GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
 111         GPIO0C6_GPIO            = 0,
 112         GPIO0C6_LCDC_D18,
 113         GPIO0C6_TRACE_D8,
 114         GPIO0C6_UART1_CTSN,
 115
 116         GPIO0C5_SHIFT           = 10,
 117         GPIO0C5_MASK            = 3 << GPIO0C5_SHIFT,
 118         GPIO0C5_GPIO            = 0,
 119         GPIO0C5_LCDC_D17,
 120         GPIO0C5_TRACE_D7,
 121         GPIO0C5_UART1_SOUT,
 122
 123         GPIO0C4_SHIFT           = 8,
 124         GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
 125         GPIO0C4_GPIO            = 0,
 126         GPIO0C4_LCDC_D16,
 127         GPIO0C4_TRACE_D6,
 128         GPIO0C4_UART1_SIN,
 129
 130         GPIO0C3_SHIFT           = 6,
 131         GPIO0C3_MASK            = 3 << GPIO0C3_SHIFT,
 132         GPIO0C3_GPIO            = 0,
 133         GPIO0C3_LCDC_D15,
 134         GPIO0C3_TRACE_D5,
 135         GPIO0C3_MCU_JTAG_TDO,
 136
 137         GPIO0C2_SHIFT           = 4,
 138         GPIO0C2_MASK            = 3 << GPIO0C2_SHIFT,
 139         GPIO0C2_GPIO            = 0,
 140         GPIO0C2_LCDC_D14,
 141         GPIO0C2_TRACE_D4,
 142         GPIO0C2_MCU_JTAG_TDI,
 143
 144         GPIO0C1_SHIFT           = 2,
 145         GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
 146         GPIO0C1_GPIO            = 0,
 147         GPIO0C1_LCDC_D13,
 148         GPIO0C1_TRACE_D3,
 149         GPIO0C1_MCU_JTAG_TRTSN,
 150
 151         GPIO0C0_SHIFT           = 0,
 152         GPIO0C0_MASK            = 3 << GPIO0C0_SHIFT,
 153         GPIO0C0_GPIO            = 0,
 154         GPIO0C0_LCDC_D12,
 155         GPIO0C0_TRACE_D2,
 156         GPIO0C0_MCU_JTAG_TDO,
 157 };
 158
 159 /*GRF_GPIO0D_IOMUX*/
 160 enum {
 161         GPIO0D7_SHIFT           = 14,
 162         GPIO0D7_MASK            = 3 << GPIO0D7_SHIFT,
 163         GPIO0D7_GPIO            = 0,
 164         GPIO0D7_LCDC_DCLK,
 165         GPIO0D7_TRACE_CTL,
 166         GPIO0D7_PMU_DEBUG5,
 167
 168         GPIO0D6_SHIFT           = 12,
 169         GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
 170         GPIO0D6_GPIO            = 0,
 171         GPIO0D6_LCDC_DEN,
 172         GPIO0D6_TRACE_CLK,
 173         GPIO0D6_PMU_DEBUG4,
 174
 175         GPIO0D5_SHIFT           = 10,
 176         GPIO0D5_MASK            = 3 << GPIO0D5_SHIFT,
 177         GPIO0D5_GPIO            = 0,
 178         GPIO0D5_LCDC_VSYNC,
 179         GPIO0D5_TRACE_D15,
 180         GPIO0D5_PMU_DEBUG3,
 181
 182         GPIO0D4_SHIFT           = 8,
 183         GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
 184         GPIO0D4_GPIO            = 0,
 185         GPIO0D4_LCDC_HSYNC,
 186         GPIO0D4_TRACE_D14,
 187         GPIO0D4_PMU_DEBUG2,
 188
 189         GPIO0D3_SHIFT           = 6,
 190         GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
 191         GPIO0D3_GPIO            = 0,
 192         GPIO0D3_LCDC_D23,
 193         GPIO0D3_TRACE_D13,
 194         GPIO0D3_UART4_SIN,
 195
 196         GPIO0D2_SHIFT           = 4,
 197         GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
 198         GPIO0D2_GPIO            = 0,
 199         GPIO0D2_LCDC_D22,
 200         GPIO0D2_TRACE_D12,
 201         GPIO0D2_UART4_SOUT,
 202
 203         GPIO0D1_SHIFT           = 2,
 204         GPIO0D1_MASK            = 3 << GPIO0D1_SHIFT,
 205         GPIO0D1_GPIO            = 0,
 206         GPIO0D1_LCDC_D21,
 207         GPIO0D1_TRACE_D11,
 208         GPIO0D1_UART4_RTSN,
 209
 210         GPIO0D0_SHIFT           = 0,
 211         GPIO0D0_MASK            = 3 << GPIO0D0_SHIFT,
 212         GPIO0D0_GPIO            = 0,
 213         GPIO0D0_LCDC_D20,
 214         GPIO0D0_TRACE_D10,
 215         GPIO0D0_UART4_CTSN,
 216 };
 217
 218 /*GRF_GPIO2A_IOMUX*/
 219 enum {
 220         GPIO2A7_SHIFT           = 14,
 221         GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
 222         GPIO2A7_GPIO            = 0,
 223         GPIO2A7_SDMMC0_D2,
 224         GPIO2A7_JTAG_TCK,
 225
 226         GPIO2A6_SHIFT           = 12,
 227         GPIO2A6_MASK            = 3 << GPIO2A6_SHIFT,
 228         GPIO2A6_GPIO            = 0,
 229         GPIO2A6_SDMMC0_D1,
 230         GPIO2A6_UART2_SIN,
 231
 232         GPIO2A5_SHIFT           = 10,
 233         GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
 234         GPIO2A5_GPIO            = 0,
 235         GPIO2A5_SDMMC0_D0,
 236         GPIO2A5_UART2_SOUT,
 237
 238         GPIO2A4_SHIFT           = 8,
 239         GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
 240         GPIO2A4_GPIO            = 0,
 241         GPIO2A4_FLASH_DQS,
 242         GPIO2A4_EMMC_CLKO,
 243
 244         GPIO2A3_SHIFT           = 6,
 245         GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
 246         GPIO2A3_GPIO            = 0,
 247         GPIO2A3_FLASH_CSN3,
 248         GPIO2A3_EMMC_RSTNO,
 249
 250         GPIO2A2_SHIFT           = 4,
 251         GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
 252         GPIO2A2_GPIO           = 0,
 253         GPIO2A2_FLASH_CSN2,
 254
 255         GPIO2A1_SHIFT           = 2,
 256         GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
 257         GPIO2A1_GPIO            = 0,
 258         GPIO2A1_FLASH_CSN1,
 259
 260         GPIO2A0_SHIFT           = 0,
 261         GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
 262         GPIO2A0_GPIO            = 0,
 263         GPIO2A0_FLASH_CSN0,
 264 };
 265
 266 /*GRF_GPIO2D_IOMUX*/
 267 enum {
 268         GPIO2D7_SHIFT           = 14,
 269         GPIO2D7_MASK            = 3 << GPIO2D7_SHIFT,
 270         GPIO2D7_GPIO            = 0,
 271         GPIO2D7_SDIO0_D3,
 272
 273         GPIO2D6_SHIFT           = 12,
 274         GPIO2D6_MASK            = 3 << GPIO2D6_SHIFT,
 275         GPIO2D6_GPIO            = 0,
 276         GPIO2D6_SDIO0_D2,
 277
 278         GPIO2D5_SHIFT           = 10,
 279         GPIO2D5_MASK            = 3 << GPIO2D5_SHIFT,
 280         GPIO2D5_GPIO            = 0,
 281         GPIO2D5_SDIO0_D1,
 282
 283         GPIO2D4_SHIFT           = 8,
 284         GPIO2D4_MASK            = 3 << GPIO2D4_SHIFT,
 285         GPIO2D4_GPIO            = 0,
 286         GPIO2D4_SDIO0_D0,
 287
 288         GPIO2D3_SHIFT           = 6,
 289         GPIO2D3_MASK            = 3 << GPIO2D3_SHIFT,
 290         GPIO2D3_GPIO            = 0,
 291         GPIO2D3_UART0_RTS0,
 292
 293         GPIO2D2_SHIFT           = 4,
 294         GPIO2D2_MASK            = 3 << GPIO2D2_SHIFT,
 295         GPIO2D2_GPIO            = 0,
 296         GPIO2D2_UART0_CTS0,
 297
 298         GPIO2D1_SHIFT           = 2,
 299         GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
 300         GPIO2D1_GPIO            = 0,
 301         GPIO2D1_UART0_SOUT,
 302
 303         GPIO2D0_SHIFT           = 0,
 304         GPIO2D0_MASK            = 3 << GPIO2D0_SHIFT,
 305         GPIO2D0_GPIO            = 0,
 306         GPIO2D0_UART0_SIN,
 307 };
 308
 309 /*GRF_GPIO3C_IOMUX*/
 310 enum {
 311         GPIO3C7_SHIFT           = 14,
 312         GPIO3C7_MASK            = 3 << GPIO3C7_SHIFT,
 313         GPIO3C7_GPIO            = 0,
 314         GPIO3C7_EDPHDMI_CECINOUT,
 315         GPIO3C7_ISP_FLASHTRIGIN,
 316
 317         GPIO3C6_SHIFT           = 12,
 318         GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
 319         GPIO3C6_GPIO            = 0,
 320         GPIO3C6_MAC_CLK,
 321         GPIO3C6_ISP_SHUTTERTRIG,
 322
 323         GPIO3C5_SHIFT           = 10,
 324         GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
 325         GPIO3C5_GPIO            = 0,
 326         GPIO3C5_MAC_RXER,
 327         GPIO3C5_ISP_PRELIGHTTRIG,
 328
 329         GPIO3C4_SHIFT           = 8,
 330         GPIO3C4_MASK            = 3 << GPIO3C4_SHIFT,
 331         GPIO3C4_GPIO            = 0,
 332         GPIO3C4_MAC_RXDV,
 333         GPIO3C4_ISP_FLASHTRIGOUT,
 334
 335         GPIO3C3_SHIFT           = 6,
 336         GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
 337         GPIO3C3_GPIO            = 0,
 338         GPIO3C3_MAC_RXDV,
 339         GPIO3C3_EMMC_RSTNO,
 340
 341         GPIO3C2_SHIFT           = 4,
 342         GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
 343         GPIO3C2_MAC_MDC            = 0,
 344         GPIO3C2_ISP_SHUTTEREN,
 345
 346         GPIO3C1_SHIFT           = 2,
 347         GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
 348         GPIO3C1_GPIO            = 0,
 349         GPIO3C1_MAC_RXD2,
 350         GPIO3C1_UART3_RTSN,
 351
 352         GPIO3C0_SHIFT           = 0,
 353         GPIO3C0_MASK            = 3 << GPIO3C0_SHIFT,
 354         GPIO3C0_GPIO            = 0,
 355         GPIO3C0_MAC_RXD1,
 356         GPIO3C0_UART3_CTSN,
 357         GPIO3C0_GPS_RFCLK,
 358 };
 359
 360 /*GRF_GPIO3D_IOMUX*/
 361 enum {
 362         GPIO3D7_SHIFT           = 14,
 363         GPIO3D7_MASK            = 3 << GPIO3D7_SHIFT,
 364         GPIO3D7_GPIO            = 0,
 365         GPIO3D7_SC_VCC18V,
 366         GPIO3D7_I2C2_SDA,
 367         GPIO3D7_GPUJTAG_TCK,
 368
 369         GPIO3D6_SHIFT           = 12,
 370         GPIO3D6_MASK            = 3 << GPIO3D6_SHIFT,
 371         GPIO3D6_GPIO            = 0,
 372         GPIO3D6_IR_TX,
 373         GPIO3D6_UART3_SOUT,
 374         GPIO3D6_PWM3,
 375
 376         GPIO3D5_SHIFT           = 10,
 377         GPIO3D5_MASK            = 3 << GPIO3D5_SHIFT,
 378         GPIO3D5_GPIO            = 0,
 379         GPIO3D5_IR_RX,
 380         GPIO3D5_UART3_SIN,
 381
 382         GPIO3D4_SHIFT           = 8,
 383         GPIO3D4_MASK            = 3 << GPIO3D4_SHIFT,
 384         GPIO3D4_GPIO            = 0,
 385         GPIO3D4_MAC_TXCLKOUT,
 386         GPIO3D4_SPI1_CSN1,
 387
 388         GPIO3D3_SHIFT           = 6,
 389         GPIO3D3_MASK            = 3 << GPIO3D3_SHIFT,
 390         GPIO3D3_GPIO            = 0,
 391         GPIO3D3_HDMII2C_SCL,
 392         GPIO3D3_I2C5_SCL,
 393
 394         GPIO3D2_SHIFT           = 4,
 395         GPIO3D2_MASK            = 3 << GPIO3D2_SHIFT,
 396         GPIO3D2_GPIO            = 0,
 397         GPIO3D2_HDMII2C_SDA,
 398         GPIO3D2_I2C5_SDA,
 399
 400         GPIO3D1_SHIFT           = 2,
 401         GPIO3D1_MASK            = 3 << GPIO3D1_SHIFT,
 402         GPIO3D1_GPIO            = 0,
 403         GPIO3D1_MAC_RXCLKIN,
 404         GPIO3D1_I2C4_SCL,
 405
 406         GPIO3D0_SHIFT           = 0,
 407         GPIO3D0_MASK            = 3 << GPIO3D0_SHIFT,
 408         GPIO3D0_GPIO            = 0,
 409         GPIO3D0_MAC_MDIO,
 410         GPIO3D0_I2C4_SDA,
 411 };
 412
 413 /*GRF_SOC_CON11/12/13*/
 414 enum {
 415         MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
 416         MCU_SRAM_BASE_BIT27_BIT12_MASK  = GENMASK(15, 0),
 417 };
 418
 419 /*GRF_SOC_CON12*/
 420 enum {
 421         MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT  = 0,
 422         MCU_EXSRAM_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
 423 };
 424
 425 /*GRF_SOC_CON13*/
 426 enum {
 427         MCU_EXPERI_BASE_BIT27_BIT12_SHIFT  = 0,
 428         MCU_EXPERI_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
 429 };
 430
 431 /*GRF_SOC_CON14*/
 432 enum {
 433         MCU_EXPERI_BASE_BIT31_BIT28_SHIFT       = 12,
 434         MCU_EXPERI_BASE_BIT31_BIT28_MASK        = GENMASK(15, 12),
 435         MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT       = 8,
 436         MCU_EXSRAM_BASE_BIT31_BIT28_MASK        = GENMASK(11, 8),
 437         MCU_SRAM_BASE_BIT31_BIT28_SHIFT         = 4,
 438         MCU_SRAM_BASE_BIT31_BIT28_MASK          = GENMASK(7, 4),
 439         MCU_CODE_BASE_BIT31_BIT28_SHIFT         = 0,
 440         MCU_CODE_BASE_BIT31_BIT28_MASK          = GENMASK(3, 0),
 441 };
 442 #endif