1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) Copyright 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
7 #ifndef _ASM_ARCH_GRF_RK3288_H
8 #define _ASM_ARCH_GRF_RK3288_H
10 struct rk3288_grf_gpio_lh {
54 struct rk3288_grf_gpio_lh gpio_sr[8];
106 u32 reserved1[(0x20-0x18)/4];
108 u32 reserved2[(0x40-0x28)/4];
110 u32 reserved3[(0x50-0x4c)/4];
127 u32 reserved4[(0x100-0x90)/4];
129 u32 reserved5[(0x120-0x108)/4];
133 /* GRF_GPIO1D_IOMUX */
156 /* GRF_GPIO2C_IOMUX */
169 /* GRF_GPIO3A_IOMUX */
174 GPIO3A7_FLASH0_DATA7,
180 GPIO3A6_FLASH0_DATA6,
186 GPIO3A5_FLASH0_DATA5,
192 GPIO3A4_FLASH0_DATA4,
198 GPIO3A3_FLASH0_DATA3,
204 GPIO3A2_FLASH0_DATA2,
210 GPIO3A1_FLASH0_DATA1,
216 GPIO3A0_FLASH0_DATA0,
220 /* GRF_GPIO3B_IOMUX */
264 /* GRF_GPIO3C_IOMUX */
276 GPIO3C1_EMMC_RSTNOUT,
285 /* GRF_GPIO3DL_IOMUX */
290 GPIO3D3_FLASH1_DATA3,
298 GPIO3D2_FLASH1_DATA2,
306 GPIO3DL1_FLASH1_DATA1,
314 GPIO3D0_FLASH1_DATA0,
320 /* GRF_GPIO3HL_IOMUX */
325 GPIO3D7_FLASH1_DATA7,
333 GPIO3D6_FLASH1_DATA6,
341 GPIO3D5_FLASH1_DATA5,
349 GPIO3D4_FLASH1_DATA4,
352 GPIO3D4_SDIO1_DETECTN,
355 /* GRF_GPIO4AL_IOMUX */
389 /* GRF_GPIO4AH_IOMUX */
397 GPIO4A7_SDIO1_CLKOUT,
423 /* GRF_GPIO4BL_IOMUX */
442 /* GRF_GPIO4C_IOMUX */
467 GPIO4C3_UART0BT_RTSN,
472 GPIO4C2_UART0BT_CTSN,
477 GPIO4C1_UART0BT_SOUT,
485 /* GRF_GPIO5B_IOMUX */
492 GPIO5B7_UART4EXP_SIN,
499 GPIO5B6_UART4EXP_SOUT,
506 GPIO5B5_UART4EXP_RTSN,
513 GPIO5B4_UART4EXP_CTSN,
518 GPIO5B3_UART1BB_RTSN,
524 GPIO5B2_UART1BB_CTSN,
530 GPIO5B1_UART1BB_SOUT,
540 /* GRF_GPIO5C_IOMUX */
564 /* GRF_GPIO6A_IOMUX */
607 /* GRF_GPIO6B_IOMUX */
617 GPIO6B2_I2C1AUDIO_SCL,
622 GPIO6B1_I2C1AUDIO_SDA,
630 /* GRF_GPIO6C_IOMUX */
635 GPIO6C6_SDMMC0_DECTN,
645 GPIO6C4_SDMMC0_CLKOUT,
651 GPIO6C3_SDMMC0_DATA3,
657 GPIO6C2_SDMMC0_DATA2,
663 GPIO6C1_SDMMC0_DATA1,
669 GPIO6C0_SDMMC0_DATA0,
673 /* GRF_GPIO7A_IOMUX */
678 GPIO7A7_UART3GPS_SIN,
680 GPIO7A7_HSADCT1_DATA0,
695 /* GRF_GPIO7B_IOMUX */
700 GPIO7B7_ISP_SHUTTERTRIG,
706 GPIO7B6_ISP_PRELIGHTTRIG,
712 GPIO7B5_ISP_FLASHTRIGOUT,
718 GPIO7B4_ISP_SHUTTEREN,
724 GPIO7B3_USB_DRVVBUS1,
730 GPIO7B2_UART3GPS_RTSN,
731 GPIO7B2_USB_DRVVBUS0,
736 GPIO7B1_UART3GPS_CTSN,
743 GPIO7B0_UART3GPS_SOUT,
745 GPIO7B0_HSADCT1_DATA1,
748 /* GRF_GPIO7CL_IOMUX */
753 GPIO7C3_I2C5HDMI_SDA,
754 GPIO7C3_EDPHDMII2C_SDA,
769 GPIO7C0_ISP_FLASHTRIGIN,
770 GPIO7C0_EDPHDMI_CECINOUTT1,
773 /* GRF_GPIO7CH_IOMUX */
778 GPIO7C7_UART2DBG_SOUT,
779 GPIO7C7_UART2DBG_SIROUT,
781 GPIO7C7_EDPHDMI_CECINOUT,
786 GPIO7C6_UART2DBG_SIN,
787 GPIO7C6_UART2DBG_SIRIN,
793 GPIO7C4_I2C5HDMI_SCL,
794 GPIO7C4_EDPHDMII2C_SCL,
797 /* GRF_GPIO8A_IOMUX */
816 GPIO8A5_I2C2SENSOR_SCL,
822 GPIO8A4_I2C2SENSOR_SDA,
849 /* GRF_GPIO8B_IOMUX */
866 PAUSE_MMC_PERI_SHIFT = 0xf,
867 PAUSE_MMC_PERI_MASK = 1,
869 PAUSE_EMEM_PERI_SHIFT = 0xe,
870 PAUSE_EMEM_PERI_MASK = 1,
872 PAUSE_USB_PERI_SHIFT = 0xd,
873 PAUSE_USB_PERI_MASK = 1,
875 GRF_FORCE_JTAG_SHIFT = 0xc,
876 GRF_FORCE_JTAG_MASK = 1,
878 GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
879 GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
881 GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
882 GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
884 DDR1_16BIT_EN_SHIFT = 9,
885 DDR1_16BIT_EN_MASK = 1,
887 DDR0_16BIT_EN_SHIFT = 8,
888 DDR0_16BIT_EN_MASK = 1,
892 VCODEC_SELECT_VEPU_ACLK = 0,
893 VCODEC_SELECT_VDPU_ACLK,
895 UPCTL1_C_ACTIVE_IN_SHIFT = 6,
896 UPCTL1_C_ACTIVE_IN_MASK = 1,
897 UPCTL1_C_ACTIVE_IN_MAY = 0,
898 UPCTL1_C_ACTIVE_IN_WILL,
900 UPCTL0_C_ACTIVE_IN_SHIFT = 5,
901 UPCTL0_C_ACTIVE_IN_MASK = 1,
902 UPCTL0_C_ACTIVE_IN_MAY = 0,
903 UPCTL0_C_ACTIVE_IN_WILL,
905 MSCH1_MAINDDR3_SHIFT = 4,
906 MSCH1_MAINDDR3_MASK = 1,
907 MSCH1_MAINDDR3_DDR3 = 1,
909 MSCH0_MAINDDR3_SHIFT = 3,
910 MSCH0_MAINDDR3_MASK = 1,
911 MSCH0_MAINDDR3_DDR3 = 1,
913 MSCH1_MAINPARTIALPOP_SHIFT = 2,
914 MSCH1_MAINPARTIALPOP_MASK = 1,
916 MSCH0_MAINPARTIALPOP_SHIFT = 1,
917 MSCH0_MAINPARTIALPOP_MASK = 1,
922 RK3288_RMII_MODE_SHIFT = 14,
923 RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT),
924 RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT),
926 RK3288_GMAC_CLK_SEL_SHIFT = 12,
927 RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
928 RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
929 RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
930 RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
932 RK3288_RMII_CLK_SEL_SHIFT = 11,
933 RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT),
934 RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT),
935 RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT),
937 GMAC_SPEED_SHIFT = 0xa,
942 GMAC_FLOWCTRL_SHIFT = 0x9,
943 GMAC_FLOWCTRL_MASK = 1,
945 RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
946 RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
947 RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
948 RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
950 HOST_REMAP_SHIFT = 0x5,
956 UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
957 UPCTL1_LPDDR3_ODT_EN_MASK = 1,
958 UPCTL1_LPDDR3_ODT_EN_ODT = 1,
960 UPCTL1_BST_DIABLE_SHIFT = 0xc,
961 UPCTL1_BST_DIABLE_MASK = 1,
962 UPCTL1_BST_DIABLE_DISABLE = 1,
964 LPDDR3_EN1_SHIFT = 0xb,
966 LPDDR3_EN1_LPDDR3 = 1,
968 UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
969 UPCTL0_LPDDR3_ODT_EN_MASK = 1,
970 UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
972 UPCTL0_BST_DIABLE_SHIFT = 9,
973 UPCTL0_BST_DIABLE_MASK = 1,
974 UPCTL0_BST_DIABLE_DISABLE = 1,
976 LPDDR3_EN0_SHIFT = 8,
978 LPDDR3_EN0_LPDDR3 = 1,
980 GRF_POC_FLASH0_CTRL_SHIFT = 7,
981 GRF_POC_FLASH0_CTRL_MASK = 1,
982 GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
983 GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
985 SIMCARD_MUX_SHIFT = 6,
986 SIMCARD_MUX_MASK = 1,
987 SIMCARD_MUX_USE_A = 1,
988 SIMCARD_MUX_USE_B = 0,
990 GRF_SPDIF_2CH_EN_SHIFT = 1,
991 GRF_SPDIF_2CH_EN_MASK = 1,
992 GRF_SPDIF_2CH_EN_8CH = 0,
993 GRF_SPDIF_2CH_EN_2CH,
1003 RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
1004 RK3288_RXCLK_DLY_ENA_GMAC_MASK =
1005 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
1006 RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
1007 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
1008 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
1010 RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
1011 RK3288_TXCLK_DLY_ENA_GMAC_MASK =
1012 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
1013 RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
1014 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
1015 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
1017 RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
1018 RK3288_CLK_RX_DL_CFG_GMAC_MASK =
1019 (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
1021 RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
1022 RK3288_CLK_TX_DL_CFG_GMAC_MASK =
1023 (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
1028 RK3288_HDMI_EDP_SEL_SHIFT = 0xf,
1029 RK3288_HDMI_EDP_SEL_MASK =
1030 1 << RK3288_HDMI_EDP_SEL_SHIFT,
1031 RK3288_HDMI_EDP_SEL_EDP = 0,
1032 RK3288_HDMI_EDP_SEL_HDMI,
1034 RK3288_DSI0_DPICOLORM_SHIFT = 0x8,
1035 RK3288_DSI0_DPICOLORM_MASK =
1036 1 << RK3288_DSI0_DPICOLORM_SHIFT,
1038 RK3288_DSI0_DPISHUTDN_SHIFT = 0x7,
1039 RK3288_DSI0_DPISHUTDN_MASK =
1040 1 << RK3288_DSI0_DPISHUTDN_SHIFT,
1042 RK3288_DSI0_LCDC_SEL_SHIFT = 0x6,
1043 RK3288_DSI0_LCDC_SEL_MASK =
1044 1 << RK3288_DSI0_LCDC_SEL_SHIFT,
1045 RK3288_DSI0_LCDC_SEL_BIG = 0,
1046 RK3288_DSI0_LCDC_SEL_LIT = 1,
1048 RK3288_EDP_LCDC_SEL_SHIFT = 0x5,
1049 RK3288_EDP_LCDC_SEL_MASK =
1050 1 << RK3288_EDP_LCDC_SEL_SHIFT,
1051 RK3288_EDP_LCDC_SEL_BIG = 0,
1052 RK3288_EDP_LCDC_SEL_LIT = 1,
1054 RK3288_HDMI_LCDC_SEL_SHIFT = 0x4,
1055 RK3288_HDMI_LCDC_SEL_MASK =
1056 1 << RK3288_HDMI_LCDC_SEL_SHIFT,
1057 RK3288_HDMI_LCDC_SEL_BIG = 0,
1058 RK3288_HDMI_LCDC_SEL_LIT = 1,
1060 RK3288_LVDS_LCDC_SEL_SHIFT = 0x3,
1061 RK3288_LVDS_LCDC_SEL_MASK =
1062 1 << RK3288_LVDS_LCDC_SEL_SHIFT,
1063 RK3288_LVDS_LCDC_SEL_BIG = 0,
1064 RK3288_LVDS_LCDC_SEL_LIT = 1,
1067 /* RK3288_SOC_CON8 */
1069 RK3288_DPHY_TX0_RXMODE_SHIFT = 4,
1070 RK3288_DPHY_TX0_RXMODE_MASK =
1071 0xf << RK3288_DPHY_TX0_RXMODE_SHIFT,
1072 RK3288_DPHY_TX0_RXMODE_EN = 0xf,
1073 RK3288_DPHY_TX0_RXMODE_DIS = 0,
1075 RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8,
1076 RK3288_DPHY_TX0_TXSTOPMODE_MASK =
1077 0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT,
1078 RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf,
1079 RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0,
1081 RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0,
1082 RK3288_DPHY_TX0_TURNREQUEST_MASK =
1083 0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT,
1084 RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf,
1085 RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
1090 GPIO1830_V18SEL_SHIFT = 9,
1091 GPIO1830_V18SEL_MASK = 1,
1092 GPIO1830_V18SEL_3_3V = 0,
1093 GPIO1830_V18SEL_1_8V,
1095 GPIO30_V18SEL_SHIFT = 8,
1096 GPIO30_V18SEL_MASK = 1,
1097 GPIO30_V18SEL_3_3V = 0,
1100 SDCARD_V18SEL_SHIFT = 7,
1101 SDCARD_V18SEL_MASK = 1,
1102 SDCARD_V18SEL_3_3V = 0,
1105 AUDIO_V18SEL_SHIFT = 6,
1106 AUDIO_V18SEL_MASK = 1,
1107 AUDIO_V18SEL_3_3V = 0,
1110 BB_V18SEL_SHIFT = 5,
1115 WIFI_V18SEL_SHIFT = 4,
1116 WIFI_V18SEL_MASK = 1,
1117 WIFI_V18SEL_3_3V = 0,
1120 FLASH1_V18SEL_SHIFT = 3,
1121 FLASH1_V18SEL_MASK = 1,
1122 FLASH1_V18SEL_3_3V = 0,
1125 FLASH0_V18SEL_SHIFT = 2,
1126 FLASH0_V18SEL_MASK = 1,
1127 FLASH0_V18SEL_3_3V = 0,
1130 DVP_V18SEL_SHIFT = 1,
1131 DVP_V18SEL_MASK = 1,
1132 DVP_V18SEL_3_3V = 0,
1135 LCDC_V18SEL_SHIFT = 0,
1136 LCDC_V18SEL_MASK = 1,
1137 LCDC_V18SEL_3_3V = 0,
1141 /* GPIO Bias settings */
1149 #define GPIO_BIAS_MASK 0x3
1150 #define GPIO_BIAS_SHIFT(x) ((x) * 2)
1152 #define GPIO_PULL_MASK 0x3
1153 #define GPIO_PULL_SHIFT(x) ((x) * 2)