arch/arm/include/asm/arch-rockchip/grf_rk3288.h

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  * Copyright 2014 Rockchip Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  */
   7
   8 #ifndef _ASM_ARCH_GRF_RK3288_H
   9 #define _ASM_ARCH_GRF_RK3288_H
  10
  11 struct rk3288_grf_gpio_lh {
  12         u32 l;
  13         u32 h;
  14 };
  15
  16 struct rk3288_grf {
  17         u32 reserved[3];
  18         u32 gpio1d_iomux;
  19         u32 gpio2a_iomux;
  20         u32 gpio2b_iomux;
  21
  22         u32 gpio2c_iomux;
  23         u32 reserved2;
  24         u32 gpio3a_iomux;
  25         u32 gpio3b_iomux;
  26
  27         u32 gpio3c_iomux;
  28         u32 gpio3dl_iomux;
  29         u32 gpio3dh_iomux;
  30         u32 gpio4al_iomux;
  31
  32         u32 gpio4ah_iomux;
  33         u32 gpio4bl_iomux;
  34         u32 reserved3;
  35         u32 gpio4c_iomux;
  36
  37         u32 gpio4d_iomux;
  38         u32 reserved4;
  39         u32 gpio5b_iomux;
  40         u32 gpio5c_iomux;
  41
  42         u32 reserved5;
  43         u32 gpio6a_iomux;
  44         u32 gpio6b_iomux;
  45         u32 gpio6c_iomux;
  46         u32 reserved6;
  47         u32 gpio7a_iomux;
  48         u32 gpio7b_iomux;
  49         u32 gpio7cl_iomux;
  50         u32 gpio7ch_iomux;
  51         u32 reserved7;
  52         u32 gpio8a_iomux;
  53         u32 gpio8b_iomux;
  54         u32 reserved8[30];
  55         struct rk3288_grf_gpio_lh gpio_sr[8];
  56         u32 gpio1_p[8][4];
  57         u32 gpio1_e[8][4];
  58         u32 gpio_smt;
  59         u32 soc_con0;
  60         u32 soc_con1;
  61         u32 soc_con2;
  62         u32 soc_con3;
  63         u32 soc_con4;
  64         u32 soc_con5;
  65         u32 soc_con6;
  66         u32 soc_con7;
  67         u32 soc_con8;
  68         u32 soc_con9;
  69         u32 soc_con10;
  70         u32 soc_con11;
  71         u32 soc_con12;
  72         u32 soc_con13;
  73         u32 soc_con14;
  74         u32 soc_status[22];
  75         u32 reserved9[2];
  76         u32 peridmac_con[4];
  77         u32 ddrc0_con0;
  78         u32 ddrc1_con0;
  79         u32 cpu_con[5];
  80         u32 reserved10[3];
  81         u32 cpu_status0;
  82         u32 reserved11;
  83         u32 uoc0_con[5];
  84         u32 uoc1_con[5];
  85         u32 uoc2_con[4];
  86         u32 uoc3_con[2];
  87         u32 uoc4_con[2];
  88         u32 pvtm_con[3];
  89         u32 pvtm_status[3];
  90         u32 io_vsel;
  91         u32 saradc_testbit;
  92         u32 tsadc_testbit_l;
  93         u32 tsadc_testbit_h;
  94         u32 os_reg[4];
  95         u32 reserved12;
  96         u32 soc_con15;
  97         u32 soc_con16;
  98 };
  99
 100 struct rk3288_sgrf {
 101         u32 soc_con0;
 102         u32 soc_con1;
 103         u32 soc_con2;
 104         u32 soc_con3;
 105         u32 soc_con4;
 106         u32 soc_con5;
 107         u32 reserved1[(0x20-0x18)/4];
 108         u32 busdmac_con[2];
 109         u32 reserved2[(0x40-0x28)/4];
 110         u32 cpu_con[3];
 111         u32 reserved3[(0x50-0x4c)/4];
 112         u32 soc_con6;
 113         u32 soc_con7;
 114         u32 soc_con8;
 115         u32 soc_con9;
 116         u32 soc_con10;
 117         u32 soc_con11;
 118         u32 soc_con12;
 119         u32 soc_con13;
 120         u32 soc_con14;
 121         u32 soc_con15;
 122         u32 soc_con16;
 123         u32 soc_con17;
 124         u32 soc_con18;
 125         u32 soc_con19;
 126         u32 soc_con20;
 127         u32 soc_con21;
 128         u32 reserved4[(0x100-0x90)/4];
 129         u32 soc_status[2];
 130         u32 reserved5[(0x120-0x108)/4];
 131         u32 fast_boot_addr;
 132 };
 133
 134 /* GRF_GPIO1D_IOMUX */
 135 enum {
 136         GPIO1D3_SHIFT           = 6,
 137         GPIO1D3_MASK            = 1,
 138         GPIO1D3_GPIO            = 0,
 139         GPIO1D3_LCDC0_DCLK,
 140
 141         GPIO1D2_SHIFT           = 4,
 142         GPIO1D2_MASK            = 1,
 143         GPIO1D2_GPIO            = 0,
 144         GPIO1D2_LCDC0_DEN,
 145
 146         GPIO1D1_SHIFT           = 2,
 147         GPIO1D1_MASK            = 1,
 148         GPIO1D1_GPIO            = 0,
 149         GPIO1D1_LCDC0_VSYNC,
 150
 151         GPIO1D0_SHIFT           = 0,
 152         GPIO1D0_MASK            = 1,
 153         GPIO1D0_GPIO            = 0,
 154         GPIO1D0_LCDC0_HSYNC,
 155 };
 156
 157 /* GRF_GPIO2C_IOMUX */
 158 enum {
 159         GPIO2C1_SHIFT           = 2,
 160         GPIO2C1_MASK            = 1,
 161         GPIO2C1_GPIO            = 0,
 162         GPIO2C1_I2C3CAM_SDA,
 163
 164         GPIO2C0_SHIFT           = 0,
 165         GPIO2C0_MASK            = 1,
 166         GPIO2C0_GPIO            = 0,
 167         GPIO2C0_I2C3CAM_SCL,
 168 };
 169
 170 /* GRF_GPIO3A_IOMUX */
 171 enum {
 172         GPIO3A7_SHIFT           = 14,
 173         GPIO3A7_MASK            = 3,
 174         GPIO3A7_GPIO            = 0,
 175         GPIO3A7_FLASH0_DATA7,
 176         GPIO3A7_EMMC_DATA7,
 177
 178         GPIO3A6_SHIFT           = 12,
 179         GPIO3A6_MASK            = 3,
 180         GPIO3A6_GPIO            = 0,
 181         GPIO3A6_FLASH0_DATA6,
 182         GPIO3A6_EMMC_DATA6,
 183
 184         GPIO3A5_SHIFT           = 10,
 185         GPIO3A5_MASK            = 3,
 186         GPIO3A5_GPIO            = 0,
 187         GPIO3A5_FLASH0_DATA5,
 188         GPIO3A5_EMMC_DATA5,
 189
 190         GPIO3A4_SHIFT           = 8,
 191         GPIO3A4_MASK            = 3,
 192         GPIO3A4_GPIO            = 0,
 193         GPIO3A4_FLASH0_DATA4,
 194         GPIO3A4_EMMC_DATA4,
 195
 196         GPIO3A3_SHIFT           = 6,
 197         GPIO3A3_MASK            = 3,
 198         GPIO3A3_GPIO            = 0,
 199         GPIO3A3_FLASH0_DATA3,
 200         GPIO3A3_EMMC_DATA3,
 201
 202         GPIO3A2_SHIFT           = 4,
 203         GPIO3A2_MASK            = 3,
 204         GPIO3A2_GPIO            = 0,
 205         GPIO3A2_FLASH0_DATA2,
 206         GPIO3A2_EMMC_DATA2,
 207
 208         GPIO3A1_SHIFT           = 2,
 209         GPIO3A1_MASK            = 3,
 210         GPIO3A1_GPIO            = 0,
 211         GPIO3A1_FLASH0_DATA1,
 212         GPIO3A1_EMMC_DATA1,
 213
 214         GPIO3A0_SHIFT           = 0,
 215         GPIO3A0_MASK            = 3,
 216         GPIO3A0_GPIO            = 0,
 217         GPIO3A0_FLASH0_DATA0,
 218         GPIO3A0_EMMC_DATA0,
 219 };
 220
 221 /* GRF_GPIO3B_IOMUX */
 222 enum {
 223         GPIO3B7_SHIFT           = 14,
 224         GPIO3B7_MASK            = 1,
 225         GPIO3B7_GPIO            = 0,
 226         GPIO3B7_FLASH0_CSN1,
 227
 228         GPIO3B6_SHIFT           = 12,
 229         GPIO3B6_MASK            = 1,
 230         GPIO3B6_GPIO            = 0,
 231         GPIO3B6_FLASH0_CSN0,
 232
 233         GPIO3B5_SHIFT           = 10,
 234         GPIO3B5_MASK            = 1,
 235         GPIO3B5_GPIO            = 0,
 236         GPIO3B5_FLASH0_WRN,
 237
 238         GPIO3B4_SHIFT           = 8,
 239         GPIO3B4_MASK            = 1,
 240         GPIO3B4_GPIO            = 0,
 241         GPIO3B4_FLASH0_CLE,
 242
 243         GPIO3B3_SHIFT           = 6,
 244         GPIO3B3_MASK            = 1,
 245         GPIO3B3_GPIO            = 0,
 246         GPIO3B3_FLASH0_ALE,
 247
 248         GPIO3B2_SHIFT           = 4,
 249         GPIO3B2_MASK            = 1,
 250         GPIO3B2_GPIO            = 0,
 251         GPIO3B2_FLASH0_RDN,
 252
 253         GPIO3B1_SHIFT           = 2,
 254         GPIO3B1_MASK            = 3,
 255         GPIO3B1_GPIO            = 0,
 256         GPIO3B1_FLASH0_WP,
 257         GPIO3B1_EMMC_PWREN,
 258
 259         GPIO3B0_SHIFT           = 0,
 260         GPIO3B0_MASK            = 1,
 261         GPIO3B0_GPIO            = 0,
 262         GPIO3B0_FLASH0_RDY,
 263 };
 264
 265 /* GRF_GPIO3C_IOMUX */
 266 enum {
 267         GPIO3C2_SHIFT           = 4,
 268         GPIO3C2_MASK            = 3,
 269         GPIO3C2_GPIO            = 0,
 270         GPIO3C2_FLASH0_DQS,
 271         GPIO3C2_EMMC_CLKOUT,
 272
 273         GPIO3C1_SHIFT           = 2,
 274         GPIO3C1_MASK            = 3,
 275         GPIO3C1_GPIO            = 0,
 276         GPIO3C1_FLASH0_CSN3,
 277         GPIO3C1_EMMC_RSTNOUT,
 278
 279         GPIO3C0_SHIFT           = 0,
 280         GPIO3C0_MASK            = 3,
 281         GPIO3C0_GPIO            = 0,
 282         GPIO3C0_FLASH0_CSN2,
 283         GPIO3C0_EMMC_CMD,
 284 };
 285
 286 /* GRF_GPIO3DL_IOMUX */
 287 enum {
 288         GPIO3D3_SHIFT           = 12,
 289         GPIO3D3_MASK            = 7,
 290         GPIO3D3_GPIO            = 0,
 291         GPIO3D3_FLASH1_DATA3,
 292         GPIO3D3_HOST_DOUT3,
 293         GPIO3D3_MAC_RXD3,
 294         GPIO3D3_SDIO1_DATA3,
 295
 296         GPIO3D2_SHIFT           = 8,
 297         GPIO3D2_MASK            = 7,
 298         GPIO3D2_GPIO            = 0,
 299         GPIO3D2_FLASH1_DATA2,
 300         GPIO3D2_HOST_DOUT2,
 301         GPIO3D2_MAC_RXD2,
 302         GPIO3D2_SDIO1_DATA2,
 303
 304         GPIO3D1_SHIFT           = 4,
 305         GPIO3D1_MASK            = 7,
 306         GPIO3D1_GPIO            = 0,
 307         GPIO3DL1_FLASH1_DATA1,
 308         GPIO3D1_HOST_DOUT1,
 309         GPIO3D1_MAC_TXD3,
 310         GPIO3D1_SDIO1_DATA1,
 311
 312         GPIO3D0_SHIFT           = 0,
 313         GPIO3D0_MASK            = 7,
 314         GPIO3D0_GPIO            = 0,
 315         GPIO3D0_FLASH1_DATA0,
 316         GPIO3D0_HOST_DOUT0,
 317         GPIO3D0_MAC_TXD2,
 318         GPIO3D0_SDIO1_DATA0,
 319 };
 320
 321 /* GRF_GPIO3HL_IOMUX */
 322 enum {
 323         GPIO3D7_SHIFT           = 12,
 324         GPIO3D7_MASK            = 7,
 325         GPIO3D7_GPIO            = 0,
 326         GPIO3D7_FLASH1_DATA7,
 327         GPIO3D7_HOST_DOUT7,
 328         GPIO3D7_MAC_RXD1,
 329         GPIO3D7_SDIO1_INTN,
 330
 331         GPIO3D6_SHIFT           = 8,
 332         GPIO3D6_MASK            = 7,
 333         GPIO3D6_GPIO            = 0,
 334         GPIO3D6_FLASH1_DATA6,
 335         GPIO3D6_HOST_DOUT6,
 336         GPIO3D6_MAC_RXD0,
 337         GPIO3D6_SDIO1_BKPWR,
 338
 339         GPIO3D5_SHIFT           = 4,
 340         GPIO3D5_MASK            = 7,
 341         GPIO3D5_GPIO            = 0,
 342         GPIO3D5_FLASH1_DATA5,
 343         GPIO3D5_HOST_DOUT5,
 344         GPIO3D5_MAC_TXD1,
 345         GPIO3D5_SDIO1_WRPRT,
 346
 347         GPIO3D4_SHIFT           = 0,
 348         GPIO3D4_MASK            = 7,
 349         GPIO3D4_GPIO            = 0,
 350         GPIO3D4_FLASH1_DATA4,
 351         GPIO3D4_HOST_DOUT4,
 352         GPIO3D4_MAC_TXD0,
 353         GPIO3D4_SDIO1_DETECTN,
 354 };
 355
 356 /* GRF_GPIO4AL_IOMUX */
 357 enum {
 358         GPIO4A3_SHIFT           = 12,
 359         GPIO4A3_MASK            = 7,
 360         GPIO4A3_GPIO            = 0,
 361         GPIO4A3_FLASH1_ALE,
 362         GPIO4A3_HOST_DOUT9,
 363         GPIO4A3_MAC_CLK,
 364         GPIO4A3_FLASH0_CSN6,
 365
 366         GPIO4A2_SHIFT           = 8,
 367         GPIO4A2_MASK            = 7,
 368         GPIO4A2_GPIO            = 0,
 369         GPIO4A2_FLASH1_RDN,
 370         GPIO4A2_HOST_DOUT8,
 371         GPIO4A2_MAC_RXER,
 372         GPIO4A2_FLASH0_CSN5,
 373
 374         GPIO4A1_SHIFT           = 4,
 375         GPIO4A1_MASK            = 7,
 376         GPIO4A1_GPIO            = 0,
 377         GPIO4A1_FLASH1_WP,
 378         GPIO4A1_HOST_CKOUTN,
 379         GPIO4A1_MAC_TXDV,
 380         GPIO4A1_FLASH0_CSN4,
 381
 382         GPIO4A0_SHIFT           = 0,
 383         GPIO4A0_MASK            = 3,
 384         GPIO4A0_GPIO            = 0,
 385         GPIO4A0_FLASH1_RDY,
 386         GPIO4A0_HOST_CKOUTP,
 387         GPIO4A0_MAC_MDC,
 388 };
 389
 390 /* GRF_GPIO4AH_IOMUX */
 391 enum {
 392         GPIO4A7_SHIFT           = 12,
 393         GPIO4A7_MASK            = 7,
 394         GPIO4A7_GPIO            = 0,
 395         GPIO4A7_FLASH1_CSN1,
 396         GPIO4A7_HOST_DOUT13,
 397         GPIO4A7_MAC_CSR,
 398         GPIO4A7_SDIO1_CLKOUT,
 399
 400         GPIO4A6_SHIFT           = 8,
 401         GPIO4A6_MASK            = 7,
 402         GPIO4A6_GPIO            = 0,
 403         GPIO4A6_FLASH1_CSN0,
 404         GPIO4A6_HOST_DOUT12,
 405         GPIO4A6_MAC_RXCLK,
 406         GPIO4A6_SDIO1_CMD,
 407
 408         GPIO4A5_SHIFT           = 4,
 409         GPIO4A5_MASK            = 3,
 410         GPIO4A5_GPIO            = 0,
 411         GPIO4A5_FLASH1_WRN,
 412         GPIO4A5_HOST_DOUT11,
 413         GPIO4A5_MAC_MDIO,
 414
 415         GPIO4A4_SHIFT           = 0,
 416         GPIO4A4_MASK            = 7,
 417         GPIO4A4_GPIO            = 0,
 418         GPIO4A4_FLASH1_CLE,
 419         GPIO4A4_HOST_DOUT10,
 420         GPIO4A4_MAC_TXEN,
 421         GPIO4A4_FLASH0_CSN7,
 422 };
 423
 424 /* GRF_GPIO4BL_IOMUX */
 425 enum {
 426         GPIO4B1_SHIFT           = 4,
 427         GPIO4B1_MASK            = 7,
 428         GPIO4B1_GPIO            = 0,
 429         GPIO4B1_FLASH1_CSN2,
 430         GPIO4B1_HOST_DOUT15,
 431         GPIO4B1_MAC_TXCLK,
 432         GPIO4B1_SDIO1_PWREN,
 433
 434         GPIO4B0_SHIFT           = 0,
 435         GPIO4B0_MASK            = 7,
 436         GPIO4B0_GPIO            = 0,
 437         GPIO4B0_FLASH1_DQS,
 438         GPIO4B0_HOST_DOUT14,
 439         GPIO4B0_MAC_COL,
 440         GPIO4B0_FLASH1_CSN3,
 441 };
 442
 443 /* GRF_GPIO4C_IOMUX */
 444 enum {
 445         GPIO4C7_SHIFT           = 14,
 446         GPIO4C7_MASK            = 1,
 447         GPIO4C7_GPIO            = 0,
 448         GPIO4C7_SDIO0_DATA3,
 449
 450         GPIO4C6_SHIFT           = 12,
 451         GPIO4C6_MASK            = 1,
 452         GPIO4C6_GPIO            = 0,
 453         GPIO4C6_SDIO0_DATA2,
 454
 455         GPIO4C5_SHIFT           = 10,
 456         GPIO4C5_MASK            = 1,
 457         GPIO4C5_GPIO            = 0,
 458         GPIO4C5_SDIO0_DATA1,
 459
 460         GPIO4C4_SHIFT           = 8,
 461         GPIO4C4_MASK            = 1,
 462         GPIO4C4_GPIO            = 0,
 463         GPIO4C4_SDIO0_DATA0,
 464
 465         GPIO4C3_SHIFT           = 6,
 466         GPIO4C3_MASK            = 1,
 467         GPIO4C3_GPIO            = 0,
 468         GPIO4C3_UART0BT_RTSN,
 469
 470         GPIO4C2_SHIFT           = 4,
 471         GPIO4C2_MASK            = 1,
 472         GPIO4C2_GPIO            = 0,
 473         GPIO4C2_UART0BT_CTSN,
 474
 475         GPIO4C1_SHIFT           = 2,
 476         GPIO4C1_MASK            = 1,
 477         GPIO4C1_GPIO            = 0,
 478         GPIO4C1_UART0BT_SOUT,
 479
 480         GPIO4C0_SHIFT           = 0,
 481         GPIO4C0_MASK            = 1,
 482         GPIO4C0_GPIO            = 0,
 483         GPIO4C0_UART0BT_SIN,
 484 };
 485
 486 /* GRF_GPIO5B_IOMUX */
 487 enum {
 488         GPIO5B7_SHIFT           = 14,
 489         GPIO5B7_MASK            = 3,
 490         GPIO5B7_GPIO            = 0,
 491         GPIO5B7_SPI0_RXD,
 492         GPIO5B7_TS0_DATA7,
 493         GPIO5B7_UART4EXP_SIN,
 494
 495         GPIO5B6_SHIFT           = 12,
 496         GPIO5B6_MASK            = 3,
 497         GPIO5B6_GPIO            = 0,
 498         GPIO5B6_SPI0_TXD,
 499         GPIO5B6_TS0_DATA6,
 500         GPIO5B6_UART4EXP_SOUT,
 501
 502         GPIO5B5_SHIFT           = 10,
 503         GPIO5B5_MASK            = 3,
 504         GPIO5B5_GPIO            = 0,
 505         GPIO5B5_SPI0_CSN0,
 506         GPIO5B5_TS0_DATA5,
 507         GPIO5B5_UART4EXP_RTSN,
 508
 509         GPIO5B4_SHIFT           = 8,
 510         GPIO5B4_MASK            = 3,
 511         GPIO5B4_GPIO            = 0,
 512         GPIO5B4_SPI0_CLK,
 513         GPIO5B4_TS0_DATA4,
 514         GPIO5B4_UART4EXP_CTSN,
 515
 516         GPIO5B3_SHIFT           = 6,
 517         GPIO5B3_MASK            = 3,
 518         GPIO5B3_GPIO            = 0,
 519         GPIO5B3_UART1BB_RTSN,
 520         GPIO5B3_TS0_DATA3,
 521
 522         GPIO5B2_SHIFT           = 4,
 523         GPIO5B2_MASK            = 3,
 524         GPIO5B2_GPIO            = 0,
 525         GPIO5B2_UART1BB_CTSN,
 526         GPIO5B2_TS0_DATA2,
 527
 528         GPIO5B1_SHIFT           = 2,
 529         GPIO5B1_MASK            = 3,
 530         GPIO5B1_GPIO            = 0,
 531         GPIO5B1_UART1BB_SOUT,
 532         GPIO5B1_TS0_DATA1,
 533
 534         GPIO5B0_SHIFT           = 0,
 535         GPIO5B0_MASK            = 3,
 536         GPIO5B0_GPIO            = 0,
 537         GPIO5B0_UART1BB_SIN,
 538         GPIO5B0_TS0_DATA0,
 539 };
 540
 541 /* GRF_GPIO5C_IOMUX */
 542 enum {
 543         GPIO5C3_SHIFT           = 6,
 544         GPIO5C3_MASK            = 1,
 545         GPIO5C3_GPIO            = 0,
 546         GPIO5C3_TS0_ERR,
 547
 548         GPIO5C2_SHIFT           = 4,
 549         GPIO5C2_MASK            = 1,
 550         GPIO5C2_GPIO            = 0,
 551         GPIO5C2_TS0_CLK,
 552
 553         GPIO5C1_SHIFT           = 2,
 554         GPIO5C1_MASK            = 1,
 555         GPIO5C1_GPIO            = 0,
 556         GPIO5C1_TS0_VALID,
 557
 558         GPIO5C0_SHIFT           = 0,
 559         GPIO5C0_MASK            = 3,
 560         GPIO5C0_GPIO            = 0,
 561         GPIO5C0_SPI0_CSN1,
 562         GPIO5C0_TS0_SYNC,
 563 };
 564
 565 /* GRF_GPIO6B_IOMUX */
 566 enum {
 567         GPIO6B3_SHIFT           = 6,
 568         GPIO6B3_MASK            = 1,
 569         GPIO6B3_GPIO            = 0,
 570         GPIO6B3_SPDIF_TX,
 571
 572         GPIO6B2_SHIFT           = 4,
 573         GPIO6B2_MASK            = 1,
 574         GPIO6B2_GPIO            = 0,
 575         GPIO6B2_I2C1AUDIO_SCL,
 576
 577         GPIO6B1_SHIFT           = 2,
 578         GPIO6B1_MASK            = 1,
 579         GPIO6B1_GPIO            = 0,
 580         GPIO6B1_I2C1AUDIO_SDA,
 581
 582         GPIO6B0_SHIFT           = 0,
 583         GPIO6B0_MASK            = 1,
 584         GPIO6B0_GPIO            = 0,
 585         GPIO6B0_I2S_CLK,
 586 };
 587
 588 /* GRF_GPIO6C_IOMUX */
 589 enum {
 590         GPIO6C6_SHIFT           = 12,
 591         GPIO6C6_MASK            = 1,
 592         GPIO6C6_GPIO            = 0,
 593         GPIO6C6_SDMMC0_DECTN,
 594
 595         GPIO6C5_SHIFT           = 10,
 596         GPIO6C5_MASK            = 1,
 597         GPIO6C5_GPIO            = 0,
 598         GPIO6C5_SDMMC0_CMD,
 599
 600         GPIO6C4_SHIFT           = 8,
 601         GPIO6C4_MASK            = 3,
 602         GPIO6C4_GPIO            = 0,
 603         GPIO6C4_SDMMC0_CLKOUT,
 604         GPIO6C4_JTAG_TDO,
 605
 606         GPIO6C3_SHIFT           = 6,
 607         GPIO6C3_MASK            = 3,
 608         GPIO6C3_GPIO            = 0,
 609         GPIO6C3_SDMMC0_DATA3,
 610         GPIO6C3_JTAG_TCK,
 611
 612         GPIO6C2_SHIFT           = 4,
 613         GPIO6C2_MASK            = 3,
 614         GPIO6C2_GPIO            = 0,
 615         GPIO6C2_SDMMC0_DATA2,
 616         GPIO6C2_JTAG_TDI,
 617
 618         GPIO6C1_SHIFT           = 2,
 619         GPIO6C1_MASK            = 3,
 620         GPIO6C1_GPIO            = 0,
 621         GPIO6C1_SDMMC0_DATA1,
 622         GPIO6C1_JTAG_TRSTN,
 623
 624         GPIO6C0_SHIFT           = 0,
 625         GPIO6C0_MASK            = 3,
 626         GPIO6C0_GPIO            = 0,
 627         GPIO6C0_SDMMC0_DATA0,
 628         GPIO6C0_JTAG_TMS,
 629 };
 630
 631 /* GRF_GPIO7A_IOMUX */
 632 enum {
 633         GPIO7A7_SHIFT           = 14,
 634         GPIO7A7_MASK            = 3,
 635         GPIO7A7_GPIO            = 0,
 636         GPIO7A7_UART3GPS_SIN,
 637         GPIO7A7_GPS_MAG,
 638         GPIO7A7_HSADCT1_DATA0,
 639
 640         GPIO7A1_SHIFT           = 2,
 641         GPIO7A1_MASK            = 1,
 642         GPIO7A1_GPIO            = 0,
 643         GPIO7A1_PWM_1,
 644
 645         GPIO7A0_SHIFT           = 0,
 646         GPIO7A0_MASK            = 3,
 647         GPIO7A0_GPIO            = 0,
 648         GPIO7A0_PWM_0,
 649         GPIO7A0_VOP0_PWM,
 650         GPIO7A0_VOP1_PWM,
 651 };
 652
 653 /* GRF_GPIO7B_IOMUX */
 654 enum {
 655         GPIO7B7_SHIFT           = 14,
 656         GPIO7B7_MASK            = 3,
 657         GPIO7B7_GPIO            = 0,
 658         GPIO7B7_ISP_SHUTTERTRIG,
 659         GPIO7B7_SPI1_TXD,
 660
 661         GPIO7B6_SHIFT           = 12,
 662         GPIO7B6_MASK            = 3,
 663         GPIO7B6_GPIO            = 0,
 664         GPIO7B6_ISP_PRELIGHTTRIG,
 665         GPIO7B6_SPI1_RXD,
 666
 667         GPIO7B5_SHIFT           = 10,
 668         GPIO7B5_MASK            = 3,
 669         GPIO7B5_GPIO            = 0,
 670         GPIO7B5_ISP_FLASHTRIGOUT,
 671         GPIO7B5_SPI1_CSN0,
 672
 673         GPIO7B4_SHIFT           = 8,
 674         GPIO7B4_MASK            = 3,
 675         GPIO7B4_GPIO            = 0,
 676         GPIO7B4_ISP_SHUTTEREN,
 677         GPIO7B4_SPI1_CLK,
 678
 679         GPIO7B3_SHIFT           = 6,
 680         GPIO7B3_MASK            = 3,
 681         GPIO7B3_GPIO            = 0,
 682         GPIO7B3_USB_DRVVBUS1,
 683         GPIO7B3_EDP_HOTPLUG,
 684
 685         GPIO7B2_SHIFT           = 4,
 686         GPIO7B2_MASK            = 3,
 687         GPIO7B2_GPIO            = 0,
 688         GPIO7B2_UART3GPS_RTSN,
 689         GPIO7B2_USB_DRVVBUS0,
 690
 691         GPIO7B1_SHIFT           = 2,
 692         GPIO7B1_MASK            = 3,
 693         GPIO7B1_GPIO            = 0,
 694         GPIO7B1_UART3GPS_CTSN,
 695         GPIO7B1_GPS_RFCLK,
 696         GPIO7B1_GPST1_CLK,
 697
 698         GPIO7B0_SHIFT           = 0,
 699         GPIO7B0_MASK            = 3,
 700         GPIO7B0_GPIO            = 0,
 701         GPIO7B0_UART3GPS_SOUT,
 702         GPIO7B0_GPS_SIG,
 703         GPIO7B0_HSADCT1_DATA1,
 704 };
 705
 706 /* GRF_GPIO7CL_IOMUX */
 707 enum {
 708         GPIO7C3_SHIFT           = 12,
 709         GPIO7C3_MASK            = 3,
 710         GPIO7C3_GPIO            = 0,
 711         GPIO7C3_I2C5HDMI_SDA,
 712         GPIO7C3_EDPHDMII2C_SDA,
 713
 714         GPIO7C2_SHIFT           = 8,
 715         GPIO7C2_MASK            = 1,
 716         GPIO7C2_GPIO            = 0,
 717         GPIO7C2_I2C4TP_SCL,
 718
 719         GPIO7C1_SHIFT           = 4,
 720         GPIO7C1_MASK            = 1,
 721         GPIO7C1_GPIO            = 0,
 722         GPIO7C1_I2C4TP_SDA,
 723
 724         GPIO7C0_SHIFT           = 0,
 725         GPIO7C0_MASK            = 3,
 726         GPIO7C0_GPIO            = 0,
 727         GPIO7C0_ISP_FLASHTRIGIN,
 728         GPIO7C0_EDPHDMI_CECINOUTT1,
 729 };
 730
 731 /* GRF_GPIO7CH_IOMUX */
 732 enum {
 733         GPIO7C7_SHIFT           = 12,
 734         GPIO7C7_MASK            = 7,
 735         GPIO7C7_GPIO            = 0,
 736         GPIO7C7_UART2DBG_SOUT,
 737         GPIO7C7_UART2DBG_SIROUT,
 738         GPIO7C7_PWM_3,
 739         GPIO7C7_EDPHDMI_CECINOUT,
 740
 741         GPIO7C6_SHIFT           = 8,
 742         GPIO7C6_MASK            = 3,
 743         GPIO7C6_GPIO            = 0,
 744         GPIO7C6_UART2DBG_SIN,
 745         GPIO7C6_UART2DBG_SIRIN,
 746         GPIO7C6_PWM_2,
 747
 748         GPIO7C4_SHIFT           = 0,
 749         GPIO7C4_MASK            = 3,
 750         GPIO7C4_GPIO            = 0,
 751         GPIO7C4_I2C5HDMI_SCL,
 752         GPIO7C4_EDPHDMII2C_SCL,
 753 };
 754
 755 /* GRF_GPIO8A_IOMUX */
 756 enum {
 757         GPIO8A7_SHIFT           = 14,
 758         GPIO8A7_MASK            = 3,
 759         GPIO8A7_GPIO            = 0,
 760         GPIO8A7_SPI2_CSN0,
 761         GPIO8A7_SC_DETECT,
 762         GPIO8A7_RESERVE,
 763
 764         GPIO8A6_SHIFT           = 12,
 765         GPIO8A6_MASK            = 3,
 766         GPIO8A6_GPIO            = 0,
 767         GPIO8A6_SPI2_CLK,
 768         GPIO8A6_SC_IO,
 769         GPIO8A6_RESERVE,
 770
 771         GPIO8A5_SHIFT           = 10,
 772         GPIO8A5_MASK            = 3,
 773         GPIO8A5_GPIO            = 0,
 774         GPIO8A5_I2C2SENSOR_SCL,
 775         GPIO8A5_SC_CLK,
 776
 777         GPIO8A4_SHIFT           = 8,
 778         GPIO8A4_MASK            = 3,
 779         GPIO8A4_GPIO            = 0,
 780         GPIO8A4_I2C2SENSOR_SDA,
 781         GPIO8A4_SC_RST,
 782
 783         GPIO8A3_SHIFT           = 6,
 784         GPIO8A3_MASK            = 3,
 785         GPIO8A3_GPIO            = 0,
 786         GPIO8A3_SPI2_CSN1,
 787         GPIO8A3_SC_IOT1,
 788
 789         GPIO8A2_SHIFT           = 4,
 790         GPIO8A2_MASK            = 1,
 791         GPIO8A2_GPIO            = 0,
 792         GPIO8A2_SC_DETECTT1,
 793
 794         GPIO8A1_SHIFT           = 2,
 795         GPIO8A1_MASK            = 3,
 796         GPIO8A1_GPIO            = 0,
 797         GPIO8A1_PS2_DATA,
 798         GPIO8A1_SC_VCC33V,
 799
 800         GPIO8A0_SHIFT           = 0,
 801         GPIO8A0_MASK            = 3,
 802         GPIO8A0_GPIO            = 0,
 803         GPIO8A0_PS2_CLK,
 804         GPIO8A0_SC_VCC18V,
 805 };
 806
 807 /* GRF_GPIO8B_IOMUX */
 808 enum {
 809         GPIO8B1_SHIFT           = 2,
 810         GPIO8B1_MASK            = 3,
 811         GPIO8B1_GPIO            = 0,
 812         GPIO8B1_SPI2_TXD,
 813         GPIO8B1_SC_CLK,
 814
 815         GPIO8B0_SHIFT           = 0,
 816         GPIO8B0_MASK            = 3,
 817         GPIO8B0_GPIO            = 0,
 818         GPIO8B0_SPI2_RXD,
 819         GPIO8B0_SC_RST,
 820 };
 821
 822 /* GRF_SOC_CON0 */
 823 enum {
 824         PAUSE_MMC_PERI_SHIFT    = 0xf,
 825         PAUSE_MMC_PERI_MASK     = 1,
 826
 827         PAUSE_EMEM_PERI_SHIFT   = 0xe,
 828         PAUSE_EMEM_PERI_MASK    = 1,
 829
 830         PAUSE_USB_PERI_SHIFT    = 0xd,
 831         PAUSE_USB_PERI_MASK     = 1,
 832
 833         GRF_FORCE_JTAG_SHIFT    = 0xc,
 834         GRF_FORCE_JTAG_MASK     = 1,
 835
 836         GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
 837         GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
 838
 839         GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
 840         GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
 841
 842         DDR1_16BIT_EN_SHIFT     = 9,
 843         DDR1_16BIT_EN_MASK      = 1,
 844
 845         DDR0_16BIT_EN_SHIFT     = 8,
 846         DDR0_16BIT_EN_MASK      = 1,
 847
 848         VCODEC_SHIFT            = 7,
 849         VCODEC_MASK             = 1,
 850         VCODEC_SELECT_VEPU_ACLK = 0,
 851         VCODEC_SELECT_VDPU_ACLK,
 852
 853         UPCTL1_C_ACTIVE_IN_SHIFT = 6,
 854         UPCTL1_C_ACTIVE_IN_MASK = 1,
 855         UPCTL1_C_ACTIVE_IN_MAY  = 0,
 856         UPCTL1_C_ACTIVE_IN_WILL,
 857
 858         UPCTL0_C_ACTIVE_IN_SHIFT = 5,
 859         UPCTL0_C_ACTIVE_IN_MASK = 1,
 860         UPCTL0_C_ACTIVE_IN_MAY  = 0,
 861         UPCTL0_C_ACTIVE_IN_WILL,
 862
 863         MSCH1_MAINDDR3_SHIFT    = 4,
 864         MSCH1_MAINDDR3_MASK     = 1,
 865         MSCH1_MAINDDR3_DDR3     = 1,
 866
 867         MSCH0_MAINDDR3_SHIFT    = 3,
 868         MSCH0_MAINDDR3_MASK     = 1,
 869         MSCH0_MAINDDR3_DDR3     = 1,
 870
 871         MSCH1_MAINPARTIALPOP_SHIFT = 2,
 872         MSCH1_MAINPARTIALPOP_MASK = 1,
 873
 874         MSCH0_MAINPARTIALPOP_SHIFT = 1,
 875         MSCH0_MAINPARTIALPOP_MASK = 1,
 876 };
 877
 878 /* GRF_SOC_CON1 */
 879 enum {
 880         RK3288_RMII_MODE_SHIFT = 14,
 881         RK3288_RMII_MODE_MASK  = (1 << RK3288_RMII_MODE_SHIFT),
 882         RK3288_RMII_MODE       = (1 << RK3288_RMII_MODE_SHIFT),
 883
 884         RK3288_GMAC_CLK_SEL_SHIFT = 12,
 885         RK3288_GMAC_CLK_SEL_MASK  = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
 886         RK3288_GMAC_CLK_SEL_125M  = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
 887         RK3288_GMAC_CLK_SEL_25M   = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
 888         RK3288_GMAC_CLK_SEL_2_5M  = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
 889
 890         RK3288_RMII_CLK_SEL_SHIFT = 11,
 891         RK3288_RMII_CLK_SEL_MASK  = (1 << RK3288_RMII_CLK_SEL_SHIFT),
 892         RK3288_RMII_CLK_SEL_2_5M  = (0 << RK3288_RMII_CLK_SEL_SHIFT),
 893         RK3288_RMII_CLK_SEL_25M   = (1 << RK3288_RMII_CLK_SEL_SHIFT),
 894
 895         GMAC_SPEED_SHIFT        = 0xa,
 896         GMAC_SPEED_MASK         = 1,
 897         GMAC_SPEED_10M          = 0,
 898         GMAC_SPEED_100M,
 899
 900         GMAC_FLOWCTRL_SHIFT     = 0x9,
 901         GMAC_FLOWCTRL_MASK      = 1,
 902
 903         RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
 904         RK3288_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
 905         RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
 906         RK3288_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
 907
 908         HOST_REMAP_SHIFT        = 0x5,
 909         HOST_REMAP_MASK         = 1
 910 };
 911
 912 /* GRF_SOC_CON2 */
 913 enum {
 914         UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
 915         UPCTL1_LPDDR3_ODT_EN_MASK = 1,
 916         UPCTL1_LPDDR3_ODT_EN_ODT = 1,
 917
 918         UPCTL1_BST_DIABLE_SHIFT = 0xc,
 919         UPCTL1_BST_DIABLE_MASK  = 1,
 920         UPCTL1_BST_DIABLE_DISABLE = 1,
 921
 922         LPDDR3_EN1_SHIFT        = 0xb,
 923         LPDDR3_EN1_MASK         = 1,
 924         LPDDR3_EN1_LPDDR3       = 1,
 925
 926         UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
 927         UPCTL0_LPDDR3_ODT_EN_MASK = 1,
 928         UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
 929
 930         UPCTL0_BST_DIABLE_SHIFT = 9,
 931         UPCTL0_BST_DIABLE_MASK  = 1,
 932         UPCTL0_BST_DIABLE_DISABLE = 1,
 933
 934         LPDDR3_EN0_SHIFT        = 8,
 935         LPDDR3_EN0_MASK         = 1,
 936         LPDDR3_EN0_LPDDR3       = 1,
 937
 938         GRF_POC_FLASH0_CTRL_SHIFT = 7,
 939         GRF_POC_FLASH0_CTRL_MASK = 1,
 940         GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
 941         GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
 942
 943         SIMCARD_MUX_SHIFT       = 6,
 944         SIMCARD_MUX_MASK        = 1,
 945         SIMCARD_MUX_USE_A       = 1,
 946         SIMCARD_MUX_USE_B       = 0,
 947
 948         GRF_SPDIF_2CH_EN_SHIFT  = 1,
 949         GRF_SPDIF_2CH_EN_MASK   = 1,
 950         GRF_SPDIF_2CH_EN_8CH    = 0,
 951         GRF_SPDIF_2CH_EN_2CH,
 952
 953         PWM_SHIFT               = 0,
 954         PWM_MASK                = 1,
 955         PWM_RK                  = 1,
 956         PWM_PWM                 = 0,
 957 };
 958
 959 /* GRF_SOC_CON3 */
 960 enum {
 961         RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
 962         RK3288_RXCLK_DLY_ENA_GMAC_MASK =
 963                 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
 964         RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
 965         RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
 966                 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
 967
 968         RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
 969         RK3288_TXCLK_DLY_ENA_GMAC_MASK =
 970                 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
 971         RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
 972         RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
 973                 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
 974
 975         RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
 976         RK3288_CLK_RX_DL_CFG_GMAC_MASK =
 977                 (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
 978
 979         RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
 980         RK3288_CLK_TX_DL_CFG_GMAC_MASK =
 981                 (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
 982 };
 983
 984 /* GRF_SOC_CON6 */
 985 enum GRF_SOC_CON6 {
 986         RK3288_HDMI_EDP_SEL_SHIFT = 0xf,
 987         RK3288_HDMI_EDP_SEL_MASK =
 988                 1 << RK3288_HDMI_EDP_SEL_SHIFT,
 989         RK3288_HDMI_EDP_SEL_EDP = 0,
 990         RK3288_HDMI_EDP_SEL_HDMI,
 991
 992         RK3288_DSI0_DPICOLORM_SHIFT = 0x8,
 993         RK3288_DSI0_DPICOLORM_MASK =
 994                 1 << RK3288_DSI0_DPICOLORM_SHIFT,
 995
 996         RK3288_DSI0_DPISHUTDN_SHIFT = 0x7,
 997         RK3288_DSI0_DPISHUTDN_MASK =
 998                 1 << RK3288_DSI0_DPISHUTDN_SHIFT,
 999
1000         RK3288_DSI0_LCDC_SEL_SHIFT = 0x6,
1001         RK3288_DSI0_LCDC_SEL_MASK =
1002                 1 << RK3288_DSI0_LCDC_SEL_SHIFT,
1003         RK3288_DSI0_LCDC_SEL_BIG = 0,
1004         RK3288_DSI0_LCDC_SEL_LIT = 1,
1005
1006         RK3288_EDP_LCDC_SEL_SHIFT = 0x5,
1007         RK3288_EDP_LCDC_SEL_MASK =
1008                 1 << RK3288_EDP_LCDC_SEL_SHIFT,
1009         RK3288_EDP_LCDC_SEL_BIG = 0,
1010         RK3288_EDP_LCDC_SEL_LIT = 1,
1011
1012         RK3288_HDMI_LCDC_SEL_SHIFT = 0x4,
1013         RK3288_HDMI_LCDC_SEL_MASK =
1014                 1 << RK3288_HDMI_LCDC_SEL_SHIFT,
1015         RK3288_HDMI_LCDC_SEL_BIG = 0,
1016         RK3288_HDMI_LCDC_SEL_LIT = 1,
1017
1018         RK3288_LVDS_LCDC_SEL_SHIFT = 0x3,
1019         RK3288_LVDS_LCDC_SEL_MASK =
1020                 1 << RK3288_LVDS_LCDC_SEL_SHIFT,
1021         RK3288_LVDS_LCDC_SEL_BIG = 0,
1022         RK3288_LVDS_LCDC_SEL_LIT = 1,
1023 };
1024
1025 /* RK3288_SOC_CON8 */
1026 enum GRF_SOC_CON8 {
1027         RK3288_DPHY_TX0_RXMODE_SHIFT = 4,
1028         RK3288_DPHY_TX0_RXMODE_MASK =
1029            0xf << RK3288_DPHY_TX0_RXMODE_SHIFT,
1030         RK3288_DPHY_TX0_RXMODE_EN = 0xf,
1031         RK3288_DPHY_TX0_RXMODE_DIS = 0,
1032
1033         RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8,
1034         RK3288_DPHY_TX0_TXSTOPMODE_MASK =
1035            0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT,
1036         RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf,
1037         RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0,
1038
1039         RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0,
1040         RK3288_DPHY_TX0_TURNREQUEST_MASK =
1041            0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT,
1042         RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf,
1043         RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
1044 };
1045
1046 /* GPIO Bias settings */
1047 enum GPIO_BIAS {
1048         GPIO_BIAS_2MA = 0,
1049         GPIO_BIAS_4MA,
1050         GPIO_BIAS_8MA,
1051         GPIO_BIAS_12MA,
1052 };
1053
1054 #define GPIO_BIAS_MASK  0x3
1055 #define GPIO_BIAS_SHIFT(x)  ((x) * 2)
1056
1057 enum GPIO_PU_PD {
1058         GPIO_PULL_NORMAL = 0,
1059         GPIO_PULL_UP,
1060         GPIO_PULL_DOWN,
1061         GPIO_PULL_REPEAT,
1062 };
1063
1064 #define GPIO_PULL_MASK  0x3
1065 #define GPIO_PULL_SHIFT(x)  ((x) * 2)
1066
1067 #endif