1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
6 #ifndef _ASM_ARCH_GRF_RK3188_H
7 #define _ASM_ARCH_GRF_RK3188_H
9 struct rk3188_grf_gpio_lh {
15 struct rk3188_grf_gpio_lh gpio_dir[4];
16 struct rk3188_grf_gpio_lh gpio_do[4];
17 struct rk3188_grf_gpio_lh gpio_en[4];
69 check_member(rk3188_grf, flash_cmd_p, 0x01a4);
73 HSADC_CLK_DIR_SHIFT = 15,
74 HSADC_CLK_DIR_MASK = 1,
82 EMMC_FLASH_SEL_SHIFT = 11,
83 EMMC_FLASH_SEL_MASK = 1,
85 TZPC_REVISION_SHIFT = 7,
86 TZPC_REVISION_MASK = 0xf,
88 L2CACHE_ACC_SHIFT = 5,
94 IMEMRD_WAIT_SHIFT = 1,
100 RKI2C4_SEL_SHIFT = 15,
103 RKI2C3_SEL_SHIFT = 14,
106 RKI2C2_SEL_SHIFT = 13,
109 RKI2C1_SEL_SHIFT = 12,
112 RKI2C0_SEL_SHIFT = 11,
115 VCODEC_SEL_SHIFT = 10,
118 PERI_EMEM_PAUSE_SHIFT = 9,
119 PERI_EMEM_PAUSE_MASK = 1,
121 PERI_USB_PAUSE_SHIFT = 8,
122 PERI_USB_PAUSE_MASK = 1,
124 SMC_MUX_MODE_0_SHIFT = 6,
125 SMC_MUX_MODE_0_MASK = 1,
127 SMC_SRAM_MW_0_SHIFT = 4,
128 SMC_SRAM_MW_0_MASK = 3,
130 SMC_REMAP_0_SHIFT = 3,
131 SMC_REMAP_0_MASK = 1,
133 SMC_A_GT_M0_SYNC_SHIFT = 2,
134 SMC_A_GT_M0_SYNC_MASK = 1,
136 EMAC_SPEED_SHIFT = 1,
145 SDIO_CLK_OUT_SR_SHIFT = 15,
146 SDIO_CLK_OUT_SR_MASK = 1,
148 MEM_EMA_L2C_SHIFT = 11,
149 MEM_EMA_L2C_MASK = 7,
151 MEM_EMA_A9_SHIFT = 8,
154 MSCH4_MAINDDR3_SHIFT = 7,
155 MSCH4_MAINDDR3_MASK = 1,
156 MSCH4_MAINDDR3_DDR3 = 1,
158 EMAC_NEWRCV_EN_SHIFT = 6,
159 EMAC_NEWRCV_EN_MASK = 1,
161 SW_ADDR15_EN_SHIFT = 5,
162 SW_ADDR15_EN_MASK = 1,
164 SW_ADDR16_EN_SHIFT = 4,
165 SW_ADDR16_EN_MASK = 1,
167 SW_ADDR17_EN_SHIFT = 3,
168 SW_ADDR17_EN_MASK = 1,
170 BANK2_TO_RANK_EN_SHIFT = 2,
171 BANK2_TO_RANK_EN_MASK = 1,
173 RANK_TO_ROW15_EN_SHIFT = 1,
174 RANK_TO_ROW15_EN_MASK = 1,
176 UPCTL_C_ACTIVE_IN_SHIFT = 0,
177 UPCTL_C_ACTIVE_IN_MASK = 1,
178 UPCTL_C_ACTIVE_IN_MAY = 0,
179 UPCTL_C_ACTIVE_IN_WILL,
184 DDR_16BIT_EN_SHIFT = 15,
185 DDR_16BIT_EN_MASK = 1,
212 SIDDQ_MASK = 1 << SIDDQ_SHIFT,
215 BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT,
217 BYPASSDMEN_SHIFT = 8,
218 BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT,
220 UOC_DISABLE_SHIFT = 4,
221 UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT,
223 COMMON_ON_N_SHIFT = 0,
224 COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT,
229 SOFT_CON_SEL_SHIFT = 2,
230 SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT,
235 TERMSEL_FULLSPEED_SHIFT = 5,
236 TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT,
238 XCVRSELECT_SHIFT = 3,
239 XCVRSELECT_FSTRANSC = 1,
240 XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT,
243 OPMODE_NODRIVING = 1,
244 OPMODE_MASK = 3 << OPMODE_SHIFT,
247 SUSPENDN_MASK = 1 << SUSPENDN_SHIFT,