1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
5 #ifndef _ASM_ARCH_GRF_RK3128_H
6 #define _ASM_ARCH_GRF_RK3128_H
11 unsigned int reserved[0x2a];
12 unsigned int gpio0a_iomux;
13 unsigned int gpio0b_iomux;
14 unsigned int gpio0c_iomux;
15 unsigned int gpio0d_iomux;
16 unsigned int gpio1a_iomux;
17 unsigned int gpio1b_iomux;
18 unsigned int gpio1c_iomux;
19 unsigned int gpio1d_iomux;
20 unsigned int gpio2a_iomux;
21 unsigned int gpio2b_iomux;
22 unsigned int gpio2c_iomux;
23 unsigned int gpio2d_iomux;
24 unsigned int gpio3a_iomux;
25 unsigned int gpio3b_iomux;
26 unsigned int gpio3c_iomux;
27 unsigned int gpio3d_iomux;
28 unsigned int gpio2c_iomux2;
29 unsigned int grf_cif_iomux;
30 unsigned int grf_cif_iomux1;
31 unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
32 unsigned int gpio0l_pull;
33 unsigned int gpio0h_pull;
34 unsigned int gpio1l_pull;
35 unsigned int gpio1h_pull;
36 unsigned int gpio2l_pull;
37 unsigned int gpio2h_pull;
38 unsigned int gpio3l_pull;
39 unsigned int gpio3h_pull;
40 unsigned int reserved2;
41 unsigned int soc_con0;
42 unsigned int soc_con1;
43 unsigned int soc_con2;
44 unsigned int soc_status0;
45 unsigned int reserved3[6];
46 unsigned int mac_con0;
47 unsigned int mac_con1;
48 unsigned int reserved4[4];
49 unsigned int uoc0_con0;
50 unsigned int reserved5;
51 unsigned int uoc1_con1;
52 unsigned int uoc1_con2;
53 unsigned int uoc1_con3;
54 unsigned int uoc1_con4;
55 unsigned int uoc1_con5;
56 unsigned int reserved6;
57 unsigned int ddrc_stat;
58 unsigned int reserved9;
59 unsigned int soc_status1;
60 unsigned int cpu_con0;
61 unsigned int cpu_con1;
62 unsigned int cpu_con2;
63 unsigned int cpu_con3;
64 unsigned int reserved10;
65 unsigned int reserved11;
66 unsigned int cpu_status0;
67 unsigned int cpu_status1;
68 unsigned int os_reg[8];
69 unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
70 unsigned int usbphy0_con[8];
71 unsigned int usbphy1_con[8];
72 unsigned int uoc_status0;
73 unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
74 unsigned int chip_tag;
75 unsigned int sdmmc_det_cnt;
77 check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
80 unsigned int wakeup_cfg;
81 unsigned int pwrdn_con;
82 unsigned int pwrdn_st;
83 unsigned int idle_req;
85 unsigned int pwrmode_con;
86 unsigned int pwr_state;
88 unsigned int core_pwrdwn_cnt;
89 unsigned int core_pwrup_cnt;
91 unsigned int ddr_sref_st;
94 unsigned int sys_reg[4];
96 check_member(rk3128_pmu, int_st, 0x34);
98 /* GRF_GPIO0A_IOMUX */
101 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
106 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
111 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
116 GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
121 GPIO0A1_MASK = 1 << GPIO0A1_SHIFT,
126 GPIO0A0_MASK = 1 << GPIO0A0_SHIFT,
131 /* GRF_GPIO0B_IOMUX */
134 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
140 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
146 GPIO0B4_MASK = 1 << GPIO0B4_SHIFT,
151 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
168 /* GRF_GPIO0D_IOMUX */
171 GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
176 GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
181 GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
186 GPIO0D1_MASK = 1 << GPIO0D1_SHIFT,
191 GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
197 /* GRF_GPIO1A_IOMUX */
200 GPIO1A5_MASK = 3 << GPIO1A5_SHIFT,
206 GPIO1A4_MASK = 3 << GPIO1A4_SHIFT,
212 GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
217 GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
223 GPIO1A1_MASK = 3 << GPIO1A1_SHIFT,
233 GPIO1A0_SDMMC_CLKOUT,
238 /* GRF_GPIO1B_IOMUX */
241 GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
246 GPIO1B6_MASK = 1 << GPIO1B6_SHIFT,
251 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
257 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
263 GPIO1B0_MASK = 3 << GPIO1B0_SHIFT,
269 /* GRF_GPIO1C_IOMUX */
272 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
278 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
284 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
290 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
296 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
302 GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
307 GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
312 /* GRF_GPIO1D_IOMUX */
315 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
322 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
329 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
336 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
343 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
350 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
357 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
364 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
371 /* GRF_GPIO2A_IOMUX */
374 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
380 GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
385 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
391 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
398 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
404 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
410 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
416 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
422 /* GRF_GPIO2B_IOMUX */
425 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
432 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
439 GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
446 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
453 GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
460 GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
467 GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
474 GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
481 /* GRF_GPIO2C_IOMUX */
484 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
491 GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
498 GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
505 GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
512 /* GRF_GPIO2D_IOMUX */
515 GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
518 GPIO2D6_GMAC_COL = 4,
521 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
523 GPIO2D1_GMAC_MDC = 3,
526 /* GRF_GPIO2C_IOMUX2 */
529 GPIO2C7_MASK = 7 << GPIO2C7_SHIFT,
531 GPIO2C7_GMAC_TXD3 = 4,
534 GPIO2C6_MASK = 7 << GPIO2C6_SHIFT,
536 GPIO2C6_GMAC_TXD2 = 4,
539 GPIO2C5_MASK = 7 << GPIO2C5_SHIFT,
541 GPIO2C5_I2C2_SCL = 3,
545 GPIO2C4_MASK = 7 << GPIO2C4_SHIFT,
547 GPIO2C4_I2C2_SDA = 3,