1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) Copyright 2015 Google, Inc
6 #ifndef _ASM_ARCH_DDR_RK3288_H
7 #define _ASM_ARCH_DDR_RK3288_H
9 struct rk3288_ddr_pctl {
122 u32 dfitrrdlvlgateen;
141 u32 dfitrwrlvldelay0;
142 u32 dfitrwrlvldelay1;
143 u32 dfitrwrlvldelay2;
144 u32 dfitrrdlvldelay0;
145 u32 dfitrrdlvldelay1;
146 u32 dfitrrdlvldelay2;
147 u32 dfitrrdlvlgatedelay0;
148 u32 dfitrrdlvlgatedelay1;
149 u32 dfitrrdlvlgatedelay2;
155 check_member(rk3288_ddr_pctl, iptr, 0x03fc);
157 struct rk3288_ddr_publ_datx {
166 struct rk3288_ddr_publ {
202 struct rk3288_ddr_publ_datx datx8[4];
204 check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294);
217 check_member(rk3288_msch, devtodev, 0x003c);
220 #define DFI_INIT_START (1 << 0)
223 #define DFI_DRAM_CLK_SR_EN (1 << 0)
224 #define DFI_DRAM_CLK_DPD_EN (1 << 1)
227 #define DFI_PARITY_INTR_EN (1 << 0)
228 #define DFI_PARITY_EN (1 << 1)
231 #define TLP_RESP_TIME_SHIFT 16
232 #define LP_SR_EN (1 << 8)
233 #define LP_PD_EN (1 << 0)
235 /* PCT_DFITCTRLDELAY */
236 #define TCTRL_DELAY_TIME_SHIFT 0
238 /* PCT_DFITPHYWRDATA */
239 #define TPHY_WRDATA_TIME_SHIFT 0
241 /* PCT_DFITPHYRDLAT */
242 #define TPHY_RDLAT_TIME_SHIFT 0
244 /* PCT_DFITDRAMCLKDIS */
245 #define TDRAM_CLK_DIS_TIME_SHIFT 0
247 /* PCT_DFITDRAMCLKEN */
248 #define TDRAM_CLK_EN_TIME_SHIFT 0
251 #define RANK0_ODT_WRITE_SEL (1 << 3)
252 #define RANK1_ODT_WRITE_SEL (1 << 11)
254 /* PCTL_DFIODTCFG1 */
255 #define ODT_LEN_BL8_W_SHIFT 16
258 #define ACDLLCR_DLLDIS (1 << 31)
259 #define ACDLLCR_DLLSRST (1 << 30)
262 #define DXDLLCR_DLLDIS (1 << 31)
263 #define DXDLLCR_DLLSRST (1 << 30)
266 #define DLLGCR_SBIAS (1 << 30)
269 #define DQSRTT (1 << 9)
270 #define DQRTT (1 << 10)
273 #define PIR_INIT (1 << 0)
274 #define PIR_DLLSRST (1 << 1)
275 #define PIR_DLLLOCK (1 << 2)
276 #define PIR_ZCAL (1 << 3)
277 #define PIR_ITMSRST (1 << 4)
278 #define PIR_DRAMRST (1 << 5)
279 #define PIR_DRAMINIT (1 << 6)
280 #define PIR_QSTRN (1 << 7)
281 #define PIR_RVTRN (1 << 8)
282 #define PIR_ICPC (1 << 16)
283 #define PIR_DLLBYP (1 << 17)
284 #define PIR_CTLDINIT (1 << 18)
285 #define PIR_CLRSR (1 << 28)
286 #define PIR_LOCKBYP (1 << 29)
287 #define PIR_ZCALBYP (1 << 30)
288 #define PIR_INITBYP (1u << 31)
291 #define PGCR_DFTLMT_SHIFT 3
292 #define PGCR_DFTCMP_SHIFT 2
293 #define PGCR_DQSCFG_SHIFT 1
294 #define PGCR_ITMDMD_SHIFT 0
297 #define PGSR_IDONE (1 << 0)
298 #define PGSR_DLDONE (1 << 1)
299 #define PGSR_ZCDONE (1 << 2)
300 #define PGSR_DIDONE (1 << 3)
301 #define PGSR_DTDONE (1 << 4)
302 #define PGSR_DTERR (1 << 5)
303 #define PGSR_DTIERR (1 << 6)
304 #define PGSR_DFTERR (1 << 7)
305 #define PGSR_RVERR (1 << 8)
306 #define PGSR_RVEIRR (1 << 9)
309 #define PRT_ITMSRST_SHIFT 18
310 #define PRT_DLLLOCK_SHIFT 6
311 #define PRT_DLLSRST_SHIFT 0
314 #define PRT_DINIT0_SHIFT 0
315 #define PRT_DINIT1_SHIFT 19
318 #define PRT_DINIT2_SHIFT 0
319 #define PRT_DINIT3_SHIFT 17
322 #define DDRMD_LPDDR 0
326 #define DDRMD_LPDDR2_LPDDR3 4
328 #define DDRMD_SHIFT 0
333 #define DQSNRES_MASK 0xf
334 #define DQSNRES_SHIFT 8
335 #define DQSRES_MASK 0xf
336 #define DQSRES_SHIFT 4
339 #define TDQSCKMAX_SHIFT 27
340 #define TDQSCKMAX_MASK 7
341 #define TDQSCK_SHIFT 24
342 #define TDQSCK_MASK 7
345 #define DQSGX_SHIFT 5
347 #define DQSGE_SHIFT 8
354 #define SLEEP_STATE 3
355 #define WAKEUP_STATE 4
358 #define LP_TRIG_SHIFT 4
359 #define LP_TRIG_MASK 7
360 #define PCTL_STAT_MSK 7
367 #define LOW_POWER_ENTRY_REQ 6
368 #define LOW_POWER_EXIT_REQ 7
371 #define PD_OUTPUT_SHIFT 0
372 #define PU_OUTPUT_SHIFT 5
373 #define PD_ONDIE_SHIFT 10
374 #define PU_ONDIE_SHIFT 15
375 #define ZDEN_SHIFT 28
378 #define SBIAS_BYPASS (1 << 23)
381 #define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
382 #define PD_IDLE_SHIFT 8
383 #define MDDR_EN (2 << 22)
384 #define LPDDR2_EN (3 << 22)
385 #define DDR2_EN (0 << 5)
386 #define DDR3_EN (1 << 5)
387 #define LPDDR2_S2 (0 << 6)
388 #define LPDDR2_S4 (1 << 6)
389 #define MDDR_LPDDR2_BL_2 (0 << 20)
390 #define MDDR_LPDDR2_BL_4 (1 << 20)
391 #define MDDR_LPDDR2_BL_8 (2 << 20)
392 #define MDDR_LPDDR2_BL_16 (3 << 20)
393 #define DDR2_DDR3_BL_4 0
394 #define DDR2_DDR3_BL_8 1
395 #define TFAW_SHIFT 18
396 #define PD_EXIT_SLOW (0 << 17)
397 #define PD_EXIT_FAST (1 << 17)
398 #define PD_TYPE_SHIFT 16
399 #define BURSTLENGTH_SHIFT 20
402 #define POWER_UP_START (1 << 0)
405 #define POWER_UP_DONE (1 << 0)
420 #define LPDDR2_MA_SHIFT 4
421 #define LPDDR2_MA_MASK 0xff
422 #define LPDDR2_OP_SHIFT 12
423 #define LPDDR2_OP_MASK 0xff
425 #define START_CMD (1u << 31)
430 * [1:0] col(9+n), assume bw=2
432 #define DDRCONF_ROW_SHIFT 4
433 #define DDRCONF_COL_SHIFT 0
436 #define BUSWRTORD_SHIFT 4
437 #define BUSRDTOWR_SHIFT 2
438 #define BUSRDTORD_SHIFT 0
441 #define DDR3_DLL_DISABLE 1