2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_CRU_RV1108_H
7 #define _ASM_ARCH_CRU_RV1108_H
11 #define OSC_HZ (24 * 1000 * 1000)
13 #define APLL_HZ (600 * 1000000)
14 #define GPLL_HZ (594 * 1000000)
16 struct rv1108_clk_priv {
17 struct rv1108_cru *cru;
29 unsigned int reserved[2];
31 unsigned int clksel_con[46];
32 unsigned int reserved1[2];
33 unsigned int clkgate_con[20];
34 unsigned int reserved2[4];
35 unsigned int softrst_con[13];
36 unsigned int reserved3[3];
37 unsigned int glb_srst_fst_val;
38 unsigned int glb_srst_snd_val;
39 unsigned int glb_cnt_th;
40 unsigned int misc_con;
41 unsigned int glb_rst_con;
42 unsigned int glb_rst_st;
43 unsigned int sdmmc_con[2];
44 unsigned int sdio_con[2];
45 unsigned int emmc_con[2];
47 check_member(rv1108_cru, emmc_con[1], 0x01ec);
64 POSTDIV2_MASK = 7 << POSTDIV2_SHIFT,
66 POSTDIV1_MASK = 7 << POSTDIV1_SHIFT,
72 LOCK_STA_MASK = 1 << LOCK_STA_SHIFT,
73 FRACDIV_MASK = 0xffffff,
78 WORK_MODE_MASK = 1 << WORK_MODE_SHIFT,
82 DSMPD_MASK = 1 << DSMPD_SHIFT,
85 CORE_PLL_SEL_SHIFT = 8,
86 CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT,
87 CORE_PLL_SEL_APLL = 0,
88 CORE_PLL_SEL_GPLL = 1,
89 CORE_PLL_SEL_DPLL = 2,
90 CORE_CLK_DIV_SHIFT = 0,
91 CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT,
94 MAC_PLL_SEL_SHIFT = 12,
95 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
98 RMII_EXTCLK_SEL_SHIFT = 8,
99 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
100 MAC_CLK_DIV_MASK = 0x1f,
101 MAC_CLK_DIV_SHIFT = 0,
104 SFC_PLL_SEL_SHIFT = 7,
105 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
106 SFC_PLL_SEL_DPLL = 0,
107 SFC_PLL_SEL_GPLL = 1,
108 SFC_CLK_DIV_SHIFT = 0,
109 SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT,