arch/arm/include/asm/arch-rockchip/cru_rk3399.h

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ASM_ARCH_CRU_RK3399_H_
   8 #define __ASM_ARCH_CRU_RK3399_H_
   9
  10 #include <common.h>
  11
  12 /* Private data for the clock driver - used by rockchip_get_cru() */
  13 struct rk3399_clk_priv {
  14         struct rk3399_cru *cru;
  15         ulong rate;
  16 };
  17
  18 struct rk3399_pmuclk_priv {
  19         struct rk3399_pmucru *pmucru;
  20         ulong rate;
  21 };
  22
  23 struct rk3399_pmucru {
  24         u32 ppll_con[6];
  25         u32 reserved[0x1a];
  26         u32 pmucru_clksel[6];
  27         u32 pmucru_clkfrac_con[2];
  28         u32 reserved2[0x18];
  29         u32 pmucru_clkgate_con[3];
  30         u32 reserved3;
  31         u32 pmucru_softrst_con[2];
  32         u32 reserved4[2];
  33         u32 pmucru_rstnhold_con[2];
  34         u32 reserved5[2];
  35         u32 pmucru_gatedis_con[2];
  36 };
  37 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
  38
  39 struct rk3399_cru {
  40         u32 apll_l_con[6];
  41         u32 reserved[2];
  42         u32 apll_b_con[6];
  43         u32 reserved1[2];
  44         u32 dpll_con[6];
  45         u32 reserved2[2];
  46         u32 cpll_con[6];
  47         u32 reserved3[2];
  48         u32 gpll_con[6];
  49         u32 reserved4[2];
  50         u32 npll_con[6];
  51         u32 reserved5[2];
  52         u32 vpll_con[6];
  53         u32 reserved6[0x0a];
  54         u32 clksel_con[108];
  55         u32 reserved7[0x14];
  56         u32 clkgate_con[35];
  57         u32 reserved8[0x1d];
  58         u32 softrst_con[21];
  59         u32 reserved9[0x2b];
  60         u32 glb_srst_fst_value;
  61         u32 glb_srst_snd_value;
  62         u32 glb_cnt_th;
  63         u32 misc_con;
  64         u32 glb_rst_con;
  65         u32 glb_rst_st;
  66         u32 reserved10[0x1a];
  67         u32 sdmmc_con[2];
  68         u32 sdio0_con[2];
  69         u32 sdio1_con[2];
  70 };
  71 check_member(rk3399_cru, sdio1_con[1], 0x594);
  72 #define MHz             1000000
  73 #define KHz             1000
  74 #define OSC_HZ          (24*MHz)
  75 #define APLL_HZ         (600*MHz)
  76 #define GPLL_HZ         (594*MHz)
  77 #define CPLL_HZ         (384*MHz)
  78 #define PPLL_HZ         (676*MHz)
  79
  80 #define PMU_PCLK_HZ     (48*MHz)
  81
  82 #define ACLKM_CORE_HZ   (300*MHz)
  83 #define ATCLK_CORE_HZ   (300*MHz)
  84 #define PCLK_DBG_HZ     (100*MHz)
  85
  86 #define PERIHP_ACLK_HZ  (148500*KHz)
  87 #define PERIHP_HCLK_HZ  (148500*KHz)
  88 #define PERIHP_PCLK_HZ  (37125*KHz)
  89
  90 #define PERILP0_ACLK_HZ (99000*KHz)
  91 #define PERILP0_HCLK_HZ (99000*KHz)
  92 #define PERILP0_PCLK_HZ (49500*KHz)
  93
  94 #define PERILP1_HCLK_HZ (99000*KHz)
  95 #define PERILP1_PCLK_HZ (49500*KHz)
  96
  97 #define PWM_CLOCK_HZ    PMU_PCLK_HZ
  98
  99 enum apll_l_frequencies {
 100         APLL_L_1600_MHZ,
 101         APLL_L_600_MHZ,
 102 };
 103
 104 #endif  /* __ASM_ARCH_CRU_RK3399_H_ */