2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_CRU_RK3328_H_
8 #define __ASM_ARCH_CRU_RK3328_H_
12 struct rk3328_clk_priv {
13 struct rk3328_cru *cru;
31 u32 glb_srst_snd_value;
32 u32 glb_srst_fst_value;
34 u32 reserved6[(0x100 - 0xb4) / 4];
36 u32 reserved7[(0x200 - 0x1d4) / 4];
41 u32 reserved9[(0x380 - 0x330) / 4];
47 check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
50 #define OSC_HZ (24 * MHz)
51 #define APLL_HZ (600 * MHz)
52 #define GPLL_HZ (576 * MHz)
53 #define CPLL_HZ (594 * MHz)
55 #define CLK_CORE_HZ (600 * MHz)
56 #define ACLKM_CORE_HZ (300 * MHz)
57 #define PCLK_DBG_HZ (300 * MHz)
59 #define PERIHP_ACLK_HZ (144000 * KHz)
60 #define PERIHP_HCLK_HZ (72000 * KHz)
61 #define PERIHP_PCLK_HZ (72000 * KHz)
63 #define PWM_CLOCK_HZ (74 * MHz)
65 enum apll_frequencies {
70 #endif /* __ASM_ARCH_CRU_RK3328_H_ */