arch/arm/include/asm/arch-rockchip/cru_rk3288.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  *
   5  * (C) Copyright 2008-2014 Rockchip Electronics
   6  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
   7  */
   8 #ifndef _ASM_ARCH_CRU_RK3288_H
   9 #define _ASM_ARCH_CRU_RK3288_H
  10
  11 #define OSC_HZ          (24 * 1000 * 1000)
  12
  13 #define APLL_HZ         (1800 * 1000000)
  14 #define GPLL_HZ         (594 * 1000000)
  15 #define CPLL_HZ         (384 * 1000000)
  16 #define NPLL_HZ         (384 * 1000000)
  17
  18 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
  19 #define PD_BUS_ACLK_HZ  297000000
  20 #define PD_BUS_HCLK_HZ  148500000
  21 #define PD_BUS_PCLK_HZ  74250000
  22
  23 #define PERI_ACLK_HZ    148500000
  24 #define PERI_HCLK_HZ    148500000
  25 #define PERI_PCLK_HZ    74250000
  26
  27 /* Private data for the clock driver - used by rockchip_get_cru() */
  28 struct rk3288_clk_priv {
  29         struct rk3288_grf *grf;
  30         struct rk3288_cru *cru;
  31         ulong rate;
  32 };
  33
  34 struct rk3288_cru {
  35         struct rk3288_pll {
  36                 u32 con0;
  37                 u32 con1;
  38                 u32 con2;
  39                 u32 con3;
  40         } pll[5];
  41         u32 cru_mode_con;
  42         u32 reserved0[3];
  43         u32 cru_clksel_con[43];
  44         u32 reserved1[21];
  45         u32 cru_clkgate_con[19];
  46         u32 reserved2;
  47         u32 cru_glb_srst_fst_value;
  48         u32 cru_glb_srst_snd_value;
  49         u32 cru_softrst_con[12];
  50         u32 cru_misc_con;
  51         u32 cru_glb_cnt_th;
  52         u32 cru_glb_rst_con;
  53         u32 reserved3;
  54         u32 cru_glb_rst_st;
  55         u32 reserved4;
  56         u32 cru_sdmmc_con[2];
  57         u32 cru_sdio0_con[2];
  58         u32 cru_sdio1_con[2];
  59         u32 cru_emmc_con[2];
  60 };
  61 check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
  62
  63 /* CRU_CLKSEL11_CON */
  64 enum {
  65         HSICPHY_DIV_SHIFT       = 8,
  66         HSICPHY_DIV_MASK        = 0x3f << HSICPHY_DIV_SHIFT,
  67
  68         MMC0_PLL_SHIFT          = 6,
  69         MMC0_PLL_MASK           = 3 << MMC0_PLL_SHIFT,
  70         MMC0_PLL_SELECT_CODEC   = 0,
  71         MMC0_PLL_SELECT_GENERAL,
  72         MMC0_PLL_SELECT_24MHZ,
  73
  74         MMC0_DIV_SHIFT          = 0,
  75         MMC0_DIV_MASK           = 0x3f << MMC0_DIV_SHIFT,
  76 };
  77
  78 /* CRU_CLKSEL12_CON */
  79 enum {
  80         EMMC_PLL_SHIFT          = 0xe,
  81         EMMC_PLL_MASK           = 3 << EMMC_PLL_SHIFT,
  82         EMMC_PLL_SELECT_CODEC   = 0,
  83         EMMC_PLL_SELECT_GENERAL,
  84         EMMC_PLL_SELECT_24MHZ,
  85
  86         EMMC_DIV_SHIFT          = 8,
  87         EMMC_DIV_MASK           = 0x3f << EMMC_DIV_SHIFT,
  88
  89         SDIO0_PLL_SHIFT         = 6,
  90         SDIO0_PLL_MASK          = 3 << SDIO0_PLL_SHIFT,
  91         SDIO0_PLL_SELECT_CODEC  = 0,
  92         SDIO0_PLL_SELECT_GENERAL,
  93         SDIO0_PLL_SELECT_24MHZ,
  94
  95         SDIO0_DIV_SHIFT         = 0,
  96         SDIO0_DIV_MASK          = 0x3f << SDIO0_DIV_SHIFT,
  97 };
  98
  99 /* CRU_CLKSEL21_CON */
 100 enum {
 101         MAC_DIV_CON_SHIFT       = 0xf,
 102         MAC_DIV_CON_MASK        = 0x1f << MAC_DIV_CON_SHIFT,
 103
 104         RMII_EXTCLK_SHIFT       = 4,
 105         RMII_EXTCLK_MASK        = 1 << RMII_EXTCLK_SHIFT,
 106         RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
 107         RMII_EXTCLK_SELECT_EXT_CLK = 1,
 108
 109         EMAC_PLL_SHIFT          = 0,
 110         EMAC_PLL_MASK           = 0x3 << EMAC_PLL_SHIFT,
 111         EMAC_PLL_SELECT_NEW     = 0x0,
 112         EMAC_PLL_SELECT_CODEC   = 0x1,
 113         EMAC_PLL_SELECT_GENERAL = 0x2,
 114 };
 115
 116 /* CRU_CLKSEL25_CON */
 117 enum {
 118         SPI1_PLL_SHIFT          = 0xf,
 119         SPI1_PLL_MASK           = 1 << SPI1_PLL_SHIFT,
 120         SPI1_PLL_SELECT_CODEC   = 0,
 121         SPI1_PLL_SELECT_GENERAL,
 122
 123         SPI1_DIV_SHIFT          = 8,
 124         SPI1_DIV_MASK           = 0x7f << SPI1_DIV_SHIFT,
 125
 126         SPI0_PLL_SHIFT          = 7,
 127         SPI0_PLL_MASK           = 1 << SPI0_PLL_SHIFT,
 128         SPI0_PLL_SELECT_CODEC   = 0,
 129         SPI0_PLL_SELECT_GENERAL,
 130
 131         SPI0_DIV_SHIFT          = 0,
 132         SPI0_DIV_MASK           = 0x7f << SPI0_DIV_SHIFT,
 133 };
 134
 135 /* CRU_CLKSEL37_CON */
 136 enum {
 137         PCLK_CORE_DBG_DIV_SHIFT = 9,
 138         PCLK_CORE_DBG_DIV_MASK  = 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
 139
 140         ATCLK_CORE_DIV_CON_SHIFT = 4,
 141         ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
 142
 143         CLK_L2RAM_DIV_SHIFT     = 0,
 144         CLK_L2RAM_DIV_MASK      = 7 << CLK_L2RAM_DIV_SHIFT,
 145 };
 146
 147 /* CRU_CLKSEL39_CON */
 148 enum {
 149         ACLK_HEVC_PLL_SHIFT     = 0xe,
 150         ACLK_HEVC_PLL_MASK      = 3 << ACLK_HEVC_PLL_SHIFT,
 151         ACLK_HEVC_PLL_SELECT_CODEC = 0,
 152         ACLK_HEVC_PLL_SELECT_GENERAL,
 153         ACLK_HEVC_PLL_SELECT_NEW,
 154
 155         ACLK_HEVC_DIV_SHIFT     = 8,
 156         ACLK_HEVC_DIV_MASK      = 0x1f << ACLK_HEVC_DIV_SHIFT,
 157
 158         SPI2_PLL_SHIFT          = 7,
 159         SPI2_PLL_MASK           = 1 << SPI2_PLL_SHIFT,
 160         SPI2_PLL_SELECT_CODEC   = 0,
 161         SPI2_PLL_SELECT_GENERAL,
 162
 163         SPI2_DIV_SHIFT          = 0,
 164         SPI2_DIV_MASK           = 0x7f << SPI2_DIV_SHIFT,
 165 };
 166
 167 /* CRU_MODE_CON */
 168 enum {
 169         CRU_MODE_MASK           = 3,
 170
 171         NPLL_MODE_SHIFT         = 0xe,
 172         NPLL_MODE_MASK          = CRU_MODE_MASK << NPLL_MODE_SHIFT,
 173         NPLL_MODE_SLOW          = 0,
 174         NPLL_MODE_NORMAL,
 175         NPLL_MODE_DEEP,
 176
 177         GPLL_MODE_SHIFT         = 0xc,
 178         GPLL_MODE_MASK          = CRU_MODE_MASK << GPLL_MODE_SHIFT,
 179         GPLL_MODE_SLOW          = 0,
 180         GPLL_MODE_NORMAL,
 181         GPLL_MODE_DEEP,
 182
 183         CPLL_MODE_SHIFT         = 8,
 184         CPLL_MODE_MASK          = CRU_MODE_MASK << CPLL_MODE_SHIFT,
 185         CPLL_MODE_SLOW          = 0,
 186         CPLL_MODE_NORMAL,
 187         CPLL_MODE_DEEP,
 188
 189         DPLL_MODE_SHIFT         = 4,
 190         DPLL_MODE_MASK          = CRU_MODE_MASK << DPLL_MODE_SHIFT,
 191         DPLL_MODE_SLOW          = 0,
 192         DPLL_MODE_NORMAL,
 193         DPLL_MODE_DEEP,
 194
 195         APLL_MODE_SHIFT         = 0,
 196         APLL_MODE_MASK          = CRU_MODE_MASK << APLL_MODE_SHIFT,
 197         APLL_MODE_SLOW          = 0,
 198         APLL_MODE_NORMAL,
 199         APLL_MODE_DEEP,
 200 };
 201
 202 /* CRU_APLL_CON0 */
 203 enum {
 204         CLKR_SHIFT              = 8,
 205         CLKR_MASK               = 0x3f << CLKR_SHIFT,
 206
 207         CLKOD_SHIFT             = 0,
 208         CLKOD_MASK              = 0xf << CLKOD_SHIFT,
 209 };
 210
 211 /* CRU_APLL_CON1 */
 212 enum {
 213         LOCK_SHIFT              = 0x1f,
 214         LOCK_MASK               = 1 << LOCK_SHIFT,
 215         LOCK_UNLOCK             = 0,
 216         LOCK_LOCK,
 217
 218         CLKF_SHIFT              = 0,
 219         CLKF_MASK               = 0x1fff << CLKF_SHIFT,
 220 };
 221
 222 /* CRU_GLB_RST_ST */
 223 enum {
 224         GLB_POR_RST,
 225         FST_GLB_RST_ST          = BIT(0),
 226         SND_GLB_RST_ST          = BIT(1),
 227         FST_GLB_TSADC_RST_ST    = BIT(2),
 228         SND_GLB_TSADC_RST_ST    = BIT(3),
 229         FST_GLB_WDT_RST_ST      = BIT(4),
 230         SND_GLB_WDT_RST_ST      = BIT(5),
 231         GLB_RST_ST_MASK         = GENMASK(5, 0),
 232 };
 233
 234 #endif