arch/arm/include/asm/arch-rockchip/clock.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  */
   5
   6 #ifndef _ASM_ARCH_CLOCK_H
   7 #define _ASM_ARCH_CLOCK_H
   8
   9 /* define pll mode */
  10 #define RKCLK_PLL_MODE_SLOW             0
  11 #define RKCLK_PLL_MODE_NORMAL           1
  12 #define RKCLK_PLL_MODE_DEEP             2
  13
  14 enum {
  15         ROCKCHIP_SYSCON_NOC,
  16         ROCKCHIP_SYSCON_GRF,
  17         ROCKCHIP_SYSCON_SGRF,
  18         ROCKCHIP_SYSCON_PMU,
  19         ROCKCHIP_SYSCON_PMUGRF,
  20         ROCKCHIP_SYSCON_PMUSGRF,
  21         ROCKCHIP_SYSCON_CIC,
  22         ROCKCHIP_SYSCON_MSCH,
  23 };
  24
  25 /* Standard Rockchip clock numbers */
  26 enum rk_clk_id {
  27         CLK_OSC,
  28         CLK_ARM,
  29         CLK_DDR,
  30         CLK_CODEC,
  31         CLK_GENERAL,
  32         CLK_NEW,
  33
  34         CLK_COUNT,
  35 };
  36
  37 #define PLL(_type, _id, _con, _mode, _mshift,                   \
  38                  _lshift, _pflags, _rtable)                     \
  39         {                                                       \
  40                 .id             = _id,                          \
  41                 .type           = _type,                        \
  42                 .con_offset     = _con,                         \
  43                 .mode_offset    = _mode,                        \
  44                 .mode_shift     = _mshift,                      \
  45                 .lock_shift     = _lshift,                      \
  46                 .pll_flags      = _pflags,                      \
  47                 .rate_table     = _rtable,                      \
  48         }
  49
  50 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,      \
  51                         _postdiv2, _dsmpd, _frac)               \
  52 {                                                               \
  53         .rate   = _rate##U,                                     \
  54         .fbdiv = _fbdiv,                                        \
  55         .postdiv1 = _postdiv1,                                  \
  56         .refdiv = _refdiv,                                      \
  57         .postdiv2 = _postdiv2,                                  \
  58         .dsmpd = _dsmpd,                                        \
  59         .frac = _frac,                                          \
  60 }
  61
  62 struct rockchip_pll_rate_table {
  63         unsigned long rate;
  64         unsigned int nr;
  65         unsigned int nf;
  66         unsigned int no;
  67         unsigned int nb;
  68         /* for RK3036/RK3399 */
  69         unsigned int fbdiv;
  70         unsigned int postdiv1;
  71         unsigned int refdiv;
  72         unsigned int postdiv2;
  73         unsigned int dsmpd;
  74         unsigned int frac;
  75 };
  76
  77 enum rockchip_pll_type {
  78         pll_rk3036,
  79         pll_rk3066,
  80         pll_rk3328,
  81         pll_rk3366,
  82         pll_rk3399,
  83 };
  84
  85 struct rockchip_pll_clock {
  86         unsigned int                    id;
  87         unsigned int                    con_offset;
  88         unsigned int                    mode_offset;
  89         unsigned int                    mode_shift;
  90         unsigned int                    lock_shift;
  91         enum rockchip_pll_type          type;
  92         unsigned int                    pll_flags;
  93         struct rockchip_pll_rate_table *rate_table;
  94         unsigned int                    mode_mask;
  95 };
  96
  97 struct rockchip_cpu_rate_table {
  98         unsigned long rate;
  99         unsigned int aclk_div;
 100         unsigned int pclk_div;
 101 };
 102
 103 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
 104                           void __iomem *base, ulong clk_id,
 105                           ulong drate);
 106 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
 107                             void __iomem *base, ulong clk_id);
 108 const struct rockchip_cpu_rate_table *
 109 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
 110                           ulong rate);
 111
 112 static inline int rk_pll_id(enum rk_clk_id clk_id)
 113 {
 114         return clk_id - 1;
 115 }
 116
 117 struct sysreset_reg {
 118         unsigned int glb_srst_fst_value;
 119         unsigned int glb_srst_snd_value;
 120 };
 121
 122 /**
 123  * clk_get_divisor() - Calculate the required clock divisior
 124  *
 125  * Given an input rate and a required output_rate, calculate the Rockchip
 126  * divisor needed to achieve this.
 127  *
 128  * @input_rate:         Input clock rate in Hz
 129  * @output_rate:        Output clock rate in Hz
 130  * @return divisor register value to use
 131  */
 132 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
 133 {
 134         uint clk_div;
 135
 136         clk_div = input_rate / output_rate;
 137         clk_div = (clk_div + 1) & 0xfffe;
 138
 139         return clk_div;
 140 }
 141
 142 /**
 143  * rockchip_get_cru() - get a pointer to the clock/reset unit registers
 144  *
 145  * @return pointer to registers, or -ve error on error
 146  */
 147 void *rockchip_get_cru(void);
 148
 149 /**
 150  * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
 151  *
 152  * @return pointer to registers, or -ve error on error
 153  */
 154 void *rockchip_get_pmucru(void);
 155
 156 struct rk3288_cru;
 157 struct rk3288_grf;
 158
 159 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
 160
 161 int rockchip_get_clk(struct udevice **devp);
 162
 163 /*
 164  * rockchip_reset_bind() - Bind soft reset device as child of clock device
 165  *
 166  * @pdev: clock udevice
 167  * @reg_offset: the first offset in cru for softreset registers
 168  * @reg_number: the reg numbers of softreset registers
 169  * @return 0 success, or error value
 170  */
 171 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
 172
 173 #endif