1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) Copyright 2015 Google, Inc
6 #ifndef _ASM_ARCH_CLOCK_H
7 #define _ASM_ARCH_CLOCK_H
10 #define RKCLK_PLL_MODE_SLOW 0
11 #define RKCLK_PLL_MODE_NORMAL 1
12 #define RKCLK_PLL_MODE_DEEP 2
19 ROCKCHIP_SYSCON_PMUGRF,
20 ROCKCHIP_SYSCON_PMUSGRF,
25 /* Standard Rockchip clock numbers */
37 #define PLL(_type, _id, _con, _mode, _mshift, \
38 _lshift, _pflags, _rtable) \
43 .mode_offset = _mode, \
44 .mode_shift = _mshift, \
45 .lock_shift = _lshift, \
46 .pll_flags = _pflags, \
47 .rate_table = _rtable, \
50 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
51 _postdiv2, _dsmpd, _frac) \
55 .postdiv1 = _postdiv1, \
57 .postdiv2 = _postdiv2, \
62 struct rockchip_pll_rate_table {
68 /* for RK3036/RK3399 */
70 unsigned int postdiv1;
72 unsigned int postdiv2;
77 enum rockchip_pll_type {
85 struct rockchip_pll_clock {
87 unsigned int con_offset;
88 unsigned int mode_offset;
89 unsigned int mode_shift;
90 unsigned int lock_shift;
91 enum rockchip_pll_type type;
92 unsigned int pll_flags;
93 struct rockchip_pll_rate_table *rate_table;
94 unsigned int mode_mask;
97 struct rockchip_cpu_rate_table {
99 unsigned int aclk_div;
100 unsigned int pclk_div;
103 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
104 void __iomem *base, ulong clk_id,
106 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
107 void __iomem *base, ulong clk_id);
108 const struct rockchip_cpu_rate_table *
109 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
112 static inline int rk_pll_id(enum rk_clk_id clk_id)
117 struct sysreset_reg {
118 unsigned int glb_srst_fst_value;
119 unsigned int glb_srst_snd_value;
123 * clk_get_divisor() - Calculate the required clock divisior
125 * Given an input rate and a required output_rate, calculate the Rockchip
126 * divisor needed to achieve this.
128 * @input_rate: Input clock rate in Hz
129 * @output_rate: Output clock rate in Hz
130 * @return divisor register value to use
132 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
136 clk_div = input_rate / output_rate;
137 clk_div = (clk_div + 1) & 0xfffe;
143 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
145 * @return pointer to registers, or -ve error on error
147 void *rockchip_get_cru(void);
150 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
152 * @return pointer to registers, or -ve error on error
154 void *rockchip_get_pmucru(void);
159 void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
161 int rockchip_get_clk(struct udevice **devp);
164 * rockchip_reset_bind() - Bind soft reset device as child of clock device
166 * @pdev: clock udevice
167 * @reg_offset: the first offset in cru for softreset registers
168 * @reg_number: the reg numbers of softreset registers
169 * @return 0 success, or error value
171 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);