2 * Copyright (C) 2013,2014 Renesas Electronics Corporation
3 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
5 * SPDX-License-Identifier: GPL-2.0
8 #ifndef __EHCI_RMOBILE_H__
9 #define __EHCI_RMOBILE_H__
12 #define OHCI_OFFSET 0x00
13 #define OHCI_SIZE 0x1000
14 #define EHCI_OFFSET 0x1000
15 #define EHCI_SIZE 0x1000
17 #define EHCI_USBCMD (EHCI_OFFSET + 0x0020)
20 #define DIRPD (1 << 8)
21 #define PLL_RST (1 << 2)
22 #define PCICLK_MASK (1 << 1)
23 #define USBH_RST (1 << 0)
26 #define SERREN (1 << 8)
27 #define PERREN (1 << 6)
28 #define MASTEREN (1 << 2)
29 #define MEMEN (1 << 1)
31 /* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */
32 #define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0))
35 #define PCIWIN1_PCICMD ((1 << 3)|(1 << 1))
36 #define AHB_CFG_AHBPCI 0x40000000
37 #define AHB_CFG_HOST 0x80000000
40 #define PCIWIN2_PCICMD ((1 << 2)|(1 << 1))
43 #define USBH_PMEEN (1 << 19)
44 #define USBH_INTBEN (1 << 17)
45 #define USBH_INTAEN (1 << 16)
48 #define SMODE_READY_CTR (1 << 17)
49 #define SMODE_READ_BURST (1 << 16)
50 #define MMODE_HBUSREQ (1 << 7)
51 #define MMODE_BOUNDARY ((1 << 6)|(1 << 5))
52 #define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3))
53 #define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3))
54 #define MMODE_WR_INCR (1 << 2)
55 #define MMODE_BYTE_BURST (1 << 1)
56 #define MMODE_HTRANS (1 << 0)
59 #define PCIBUS_PARK_TIMER 0x00FF0000
60 #define PCIBUS_PARK_TIMER_SET 0x00070000
61 #define PCIBP_MODE (1 << 12)
62 #define PCIREQ7 (1 << 7)
63 #define PCIREQ6 (1 << 6)
64 #define PCIREQ5 (1 << 5)
65 #define PCIREQ4 (1 << 4)
66 #define PCIREQ3 (1 << 3)
67 #define PCIREQ2 (1 << 2)
68 #define PCIREQ1 (1 << 1)
69 #define PCIREQ0 (1 << 0)
71 #define SMSTPCR7 0xE615014C
72 #define SMSTPCR703 (1 << 3)
74 /* Init AHB master and slave functions of the host logic */
75 #define AHB_BUS_CTR_INIT \
76 (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \
77 MMODE_BYTE_BURST | MMODE_HTRANS)
79 #define USBCTR_WIN_SIZE_1GB 0x800
81 /* PCI Configuration Registers */
82 #define PCI_CONF_OHCI_OFFSET 0x10000
83 #define PCI_CONF_EHCI_OFFSET 0x10100
92 /* PCI Configuration Registers for AHB-PCI Bridge Registers */
93 #define PCI_CONF_AHBPCI_OFFSET 0x10000
94 struct ahbconf_pci_bridge {
95 u32 vid_did; /* 0x00 */
99 u32 basead; /* 0x10 */
103 u32 ssvdi_ssid; /* 0x2C */
108 /* AHB-PCI Bridge PCI Communication Registers */
109 #define AHBPCI_OFFSET 0x10800
110 struct ahbcom_pci_bridge {
111 u32 pciahb_win1_ctr; /* 0x00 */
115 u32 ahbpci_win1_ctr; /* 0x10 */
119 u32 pci_int_enable; /* 0x20 */
122 u32 ahb_bus_ctr; /* 0x30 */
125 u32 pci_arbiter_ctr; /* 0x40 */
127 u32 pci_unit_rev; /* 0x48 */
130 struct rmobile_ehci_reg {
131 u32 hciversion; /* hciversion/caplength */
132 u32 hcsparams; /* hcsparams */
133 u32 hccparams; /* hccparams */
134 u32 hcsp_portroute; /* hcsp_portroute */
135 u32 usbcmd; /* usbcmd */
136 u32 usbsts; /* usbsts */
137 u32 usbintr; /* usbintr */
138 u32 frindex; /* frindex */
139 u32 ctrldssegment; /* ctrldssegment */
140 u32 periodiclistbase; /* periodiclistbase */
141 u32 asynclistaddr; /* asynclistaddr */
143 u32 configflag; /* configflag */
144 u32 portsc; /* portsc */
147 #endif /* __EHCI_RMOBILE_H__ */