3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 /* Common APB clock register bit definitions */
13 #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
14 #define APBC_FNCLK (1<<1) /* Functional Clock Enable */
15 #define APBC_RST (1<<2) /* Reset Generation */
16 /* Functional Clock Selection Mask */
17 #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
19 /* Common APMU register bit definitions */
20 #define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
21 #define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
22 #define APMU_PERI_RST (1<<1) /* Peripheral Reset */
23 #define APMU_AXI_RST (1<<0) /* AXI Reset */
25 /* Register Base Addresses */
26 #define PANTHEON_DRAM_BASE 0xB0000000
27 #define PANTHEON_TIMER_BASE 0xD4014000
28 #define PANTHEON_WD_TIMER_BASE 0xD4080000
29 #define PANTHEON_APBC_BASE 0xD4015000
30 #define PANTHEON_UART1_BASE 0xD4017000
31 #define PANTHEON_UART2_BASE 0xD4018000
32 #define PANTHEON_GPIO_BASE 0xD4019000
33 #define PANTHEON_MFPR_BASE 0xD401E000
34 #define PANTHEON_MPMU_BASE 0xD4050000
35 #define PANTHEON_APMU_BASE 0xD4282800
36 #define PANTHEON_CPU_BASE 0xD4282C00
38 #endif /* _PANTHEON_H */