3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
25 #ifndef _PANTHEON_CPU_H
26 #define _PANTHEON_CPU_H
29 #include <asm/system.h>
32 * Main Power Management (MPMU) Registers
33 * Refer Register Datasheet 9.1
35 struct panthmpmu_registers {
38 u8 pad1[0x0200 - 0x024 - 4];
39 u32 wdtpcr; /*0x0200*/
40 u8 pad2[0x1020 - 0x200 - 4];
46 * Application Power Management (APMU) Registers
47 * Refer Register Datasheet 9.2
49 struct panthapmu_registers {
52 u8 pad1[0x00e0 - 0x054 - 4];
57 * APB Clock Reset/Control Registers
58 * Refer Register Datasheet 6.14
60 struct panthapb_registers {
64 u8 pad0[0x02c - 0x08 - 4];
66 u8 pad1[0x034 - 0x2c - 4];
71 * CPU Interface Registers
72 * Refer Register Datasheet 4.3
74 struct panthcpu_registers {
75 u32 chip_id; /* Chip Id Reg */
77 u32 cpu_conf; /* CPU Conf Reg */
79 u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
81 u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
82 u32 mcb_conf; /* MCB Conf Reg */
83 u32 sys_boot_ctl; /* Sytem Boot Control */
89 u32 panth_sdram_base(int);
90 u32 panth_sdram_size(int);
91 int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
93 #endif /* _PANTHEON_CPU_H */