3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _PANTHEON_CPU_H
10 #define _PANTHEON_CPU_H
13 #include <asm/system.h>
16 * Main Power Management (MPMU) Registers
17 * Refer Register Datasheet 9.1
19 struct panthmpmu_registers {
22 u8 pad1[0x0200 - 0x024 - 4];
23 u32 wdtpcr; /*0x0200*/
24 u8 pad2[0x1020 - 0x200 - 4];
30 * Application Power Management (APMU) Registers
31 * Refer Register Datasheet 9.2
33 struct panthapmu_registers {
36 u8 pad1[0x00e0 - 0x054 - 4];
41 * APB Clock Reset/Control Registers
42 * Refer Register Datasheet 6.14
44 struct panthapb_registers {
48 u8 pad0[0x02c - 0x08 - 4];
50 u8 pad1[0x034 - 0x2c - 4];
55 * CPU Interface Registers
56 * Refer Register Datasheet 4.3
58 struct panthcpu_registers {
59 u32 chip_id; /* Chip Id Reg */
61 u32 cpu_conf; /* CPU Conf Reg */
63 u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
65 u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
66 u32 mcb_conf; /* MCB Conf Reg */
67 u32 sys_boot_ctl; /* Sytem Boot Control */
73 u32 panth_sdram_base(int);
74 u32 panth_sdram_size(int);
75 int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
77 #endif /* _PANTHEON_CPU_H */