2 * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
4 * Based on original Kirkwood support which is
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 * Header file for Marvell's Orion SoC with Feroceon CPU core.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
30 #ifndef _ASM_ARCH_ORION5X_H
31 #define _ASM_ARCH_ORION5X_H
34 #include <asm/types.h>
36 #endif /* __ASSEMBLY__ */
38 #if defined(CONFIG_FEROCEON)
39 #include <asm/arch/cpu.h>
41 /* SOC specific definations */
42 #define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
44 /* Documented registers */
45 #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
46 #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
47 #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
48 #define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000))
49 #define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100))
50 #define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000))
51 #define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100))
52 #define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300))
53 #define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000))
54 #define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000))
55 #define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000))
56 #define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
57 #define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
59 /* Orion5x GbE controller has a single port */
60 #define MAX_MVGBE_DEVS 1
61 #define MVGBE0_BASE ORION5X_EGIGA_BASE
63 #define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
65 /* include here SoC variants. 5181, 5281, 6183 should go here when
66 adding support for them, and this comment should then be updated. */
67 #if defined(CONFIG_88F5182)
68 #include <asm/arch/mv88f5182.h>
70 #error "SOC Name not defined"
72 #endif /* CONFIG_FEROCEON */
73 #endif /* _ASM_ARCH_ORION5X_H */