2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
38 #endif /* __ASSEMBLY__ */
43 * For a full explanation of these registers and values please see
44 * the Technical Reference Manual (TRM) for any of the processors in
48 /* Slower full frequency range default timings for x32 operation*/
49 #define SDRC_SHARING 0x00000100
50 #define SDRC_MR_0_SDR 0x00000031
53 * SDRC autorefresh control values. This register consists of autorefresh
54 * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
55 * counter is a result of ( tREFI / tCK ) - 50.
57 #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
58 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
59 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
60 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
63 #define DLL_WRITEDDRCLKX2DIS 1
66 #define DLL_DLLPHASE_72 0
67 #define DLL_DLLPHASE_90 1
69 /* rkw - need to find of 90/72 degree recommendation for speed like before */
70 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
71 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
73 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
74 #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
75 #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
76 #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
77 #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
78 #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
79 #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
80 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
81 #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
83 #define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \
84 ACTIM_CTRLA_TRFC(a) | \
85 ACTIM_CTRLA_TRC(b) | \
86 ACTIM_CTRLA_TRAS(b) | \
87 ACTIM_CTRLA_TRP(d) | \
88 ACTIM_CTRLA_TRCD(e) | \
89 ACTIM_CTRLA_TRRD(f) | \
90 ACTIM_CTRLA_TDPL(g) | \
93 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
94 #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
95 #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
96 #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
97 #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
99 #define ACTIM_CTRLB(a,b,c,d) \
100 ACTIM_CTRLB_TWTR(a) | \
101 ACTIM_CTRLB_TCKE(b) | \
102 ACTIM_CTRLB_TXP(b) | \
106 * Values used in the MCFG register. Only values we use today
107 * are defined and the rest can be found in the TRM. Unless otherwise
108 * noted all fields are one bit.
110 #define V_MCFG_RAMTYPE_DDR (0x1)
111 #define V_MCFG_DEEPPD_EN (0x1 << 3)
112 #define V_MCFG_B32NOT16_32 (0x1 << 4)
113 #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
114 #define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */
115 #define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
116 #define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */
117 #define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */
119 /* Macro to construct MCFG */
121 V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \
122 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \
123 V_MCFG_BANKALLOCATION_RBC | \
124 V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
126 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
127 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
128 /* 15/6 + 18/6 = 5.5 -> 6 */
129 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
130 #define INFINEON_TRRD_165 2 /* 12/6 = 2 */
131 #define INFINEON_TRCD_165 3 /* 18/6 = 3 */
132 #define INFINEON_TRP_165 3 /* 18/6 = 3 */
133 #define INFINEON_TRAS_165 7 /* 42/6 = 7 */
134 #define INFINEON_TRC_165 10 /* 60/6 = 10 */
135 #define INFINEON_TRFC_165 12 /* 72/6 = 12 */
137 #define INFINEON_V_ACTIMA_165 \
138 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
139 INFINEON_TRAS_165, INFINEON_TRP_165, \
140 INFINEON_TRCD_165, INFINEON_TRRD_165, \
141 INFINEON_TDPL_165, INFINEON_TDAL_165)
143 #define INFINEON_TWTR_165 1
144 #define INFINEON_TCKE_165 2
145 #define INFINEON_TXP_165 2
146 #define INFINEON_XSR_165 20 /* 120/6 = 20 */
148 #define INFINEON_V_ACTIMB_165 \
149 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
150 INFINEON_TXP_165, INFINEON_XSR_165)
152 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
153 #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
154 /* 15/6 + 18/6 = 5.5 -> 6 */
155 #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
156 #define MICRON_TRRD_165 2 /* 12/6 = 2 */
157 #define MICRON_TRCD_165 3 /* 18/6 = 3 */
158 #define MICRON_TRP_165 3 /* 18/6 = 3 */
159 #define MICRON_TRAS_165 7 /* 42/6 = 7 */
160 #define MICRON_TRC_165 10 /* 60/6 = 10 */
161 #define MICRON_TRFC_165 21 /* 125/6 = 21 */
163 #define MICRON_V_ACTIMA_165 \
164 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
165 MICRON_TRAS_165, MICRON_TRP_165, \
166 MICRON_TRCD_165, MICRON_TRRD_165, \
167 MICRON_TDPL_165, MICRON_TDAL_165)
169 #define MICRON_TWTR_165 1
170 #define MICRON_TCKE_165 1
171 #define MICRON_XSR_165 23 /* 138/6 = 23 */
172 #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
174 #define MICRON_V_ACTIMB_165 \
175 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
176 MICRON_TXP_165, MICRON_XSR_165)
178 #define MICRON_RASWIDTH_165 0x2
179 #define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
181 #define MICRON_BL_165 0x2
182 #define MICRON_SIL_165 0x0
183 #define MICRON_CASL_165 0x3
184 #define MICRON_WBST_165 0x0
185 #define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \
186 (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
189 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
190 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
191 /* 15/6 + 18/6 = 5.5 -> 6 */
192 #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
193 #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
194 #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
195 #define NUMONYX_TRP_165 3 /* 18/6 = 3 */
196 #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
197 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */
198 #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
200 #define NUMONYX_V_ACTIMA_165 \
201 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
202 NUMONYX_TRAS_165, NUMONYX_TRP_165, \
203 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
204 NUMONYX_TDPL_165, NUMONYX_TDAL_165)
206 #define NUMONYX_TWTR_165 2
207 #define NUMONYX_TCKE_165 2
208 #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
209 #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
211 #define NUMONYX_V_ACTIMB_165 \
212 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
213 NUMONYX_TXP_165, NUMONYX_XSR_165)
215 #ifdef CONFIG_OMAP3_INFINEON_DDR
216 #define V_ACTIMA_165 INFINEON_V_ACTIMA_165
217 #define V_ACTIMB_165 INFINEON_V_ACTIMB_165
220 #ifdef CONFIG_OMAP3_MICRON_DDR
221 #define V_ACTIMA_165 MICRON_V_ACTIMA_165
222 #define V_ACTIMB_165 MICRON_V_ACTIMB_165
223 #define V_MCFG MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE)
224 #define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
225 #define V_MR MICRON_V_MR_165
228 #ifdef CONFIG_OMAP3_NUMONYX_DDR
229 #define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
230 #define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
233 #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
234 #error "Please choose the right DDR type in config header"
237 #if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
238 #error "Please choose the right DDR type in config header"
243 * Definitions is as per the following format
244 * #define <PART>_GPMC_CONFIG<x> <value>
246 * PART is the part name e.g. STNOR - Intel Strata Flash
247 * x is GPMC config registers from 1 to 6 (there will be 6 macros)
248 * Value is corresponding value
250 * For every valid PRCM configuration there should be only one definition of
251 * the same. if values are independent of the board, this definition will be
252 * present in this file if values are dependent on the board, then this should
253 * go into corresponding mem-boardName.h file
255 * Currently valid part Names are (PART):
256 * STNOR - Intel Strata Flash
257 * SMNAND - Samsung NAND
258 * MPDB - H4 MPDB board
260 * MNAND - Micron Large page x16 NAND
261 * ONNAND - Samsung One NAND
263 * include/configs/file.h contains the defn - for all CS we are interested
264 * #define OMAP34XX_GPMC_CSx PART
265 * #define OMAP34XX_GPMC_CSx_SIZE Size
266 * #define OMAP34XX_GPMC_CSx_MAP Map
269 * PART - Part Name as defined above
270 * SIZE - how big is the mapping to be
271 * GPMC_SIZE_128M - 0x8
272 * GPMC_SIZE_64M - 0xC
273 * GPMC_SIZE_32M - 0xE
274 * GPMC_SIZE_16M - 0xF
275 * MAP - Map this CS to which address(GPMC address space)- Absolute address
276 * >>24 before being used.
278 #define GPMC_SIZE_128M 0x8
279 #define GPMC_SIZE_64M 0xC
280 #define GPMC_SIZE_32M 0xE
281 #define GPMC_SIZE_16M 0xF
283 #define GPMC_BASEADDR_MASK 0x3F
285 #define GPMC_CS_ENABLE 0x1
287 #define SMNAND_GPMC_CONFIG1 0x00000800
288 #define SMNAND_GPMC_CONFIG2 0x00141400
289 #define SMNAND_GPMC_CONFIG3 0x00141400
290 #define SMNAND_GPMC_CONFIG4 0x0F010F01
291 #define SMNAND_GPMC_CONFIG5 0x010C1414
292 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80
293 #define SMNAND_GPMC_CONFIG7 0x00000C44
295 #define M_NAND_GPMC_CONFIG1 0x00001800
296 #define M_NAND_GPMC_CONFIG2 0x00141400
297 #define M_NAND_GPMC_CONFIG3 0x00141400
298 #define M_NAND_GPMC_CONFIG4 0x0F010F01
299 #define M_NAND_GPMC_CONFIG5 0x010C1414
300 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80
301 #define M_NAND_GPMC_CONFIG7 0x00000C44
303 #define STNOR_GPMC_CONFIG1 0x3
304 #define STNOR_GPMC_CONFIG2 0x00151501
305 #define STNOR_GPMC_CONFIG3 0x00060602
306 #define STNOR_GPMC_CONFIG4 0x11091109
307 #define STNOR_GPMC_CONFIG5 0x01141F1F
308 #define STNOR_GPMC_CONFIG6 0x000004c4
310 #define SIBNOR_GPMC_CONFIG1 0x1200
311 #define SIBNOR_GPMC_CONFIG2 0x001f1f00
312 #define SIBNOR_GPMC_CONFIG3 0x00080802
313 #define SIBNOR_GPMC_CONFIG4 0x1C091C09
314 #define SIBNOR_GPMC_CONFIG5 0x01131F1F
315 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
317 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
318 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
319 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
320 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
321 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
322 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
324 #define MPDB_GPMC_CONFIG1 0x00011000
325 #define MPDB_GPMC_CONFIG2 0x001f1f01
326 #define MPDB_GPMC_CONFIG3 0x00080803
327 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a
328 #define MPDB_GPMC_CONFIG5 0x041f1F1F
329 #define MPDB_GPMC_CONFIG6 0x1F0F04C4
331 #define P2_GPMC_CONFIG1 0x0
332 #define P2_GPMC_CONFIG2 0x0
333 #define P2_GPMC_CONFIG3 0x0
334 #define P2_GPMC_CONFIG4 0x0
335 #define P2_GPMC_CONFIG5 0x0
336 #define P2_GPMC_CONFIG6 0x0
338 #define ONENAND_GPMC_CONFIG1 0x00001200
339 #define ONENAND_GPMC_CONFIG2 0x000F0F01
340 #define ONENAND_GPMC_CONFIG3 0x00030301
341 #define ONENAND_GPMC_CONFIG4 0x0F040F04
342 #define ONENAND_GPMC_CONFIG5 0x010F1010
343 #define ONENAND_GPMC_CONFIG6 0x1F060000
345 #define NET_GPMC_CONFIG1 0x00001000
346 #define NET_GPMC_CONFIG2 0x001e1e01
347 #define NET_GPMC_CONFIG3 0x00080300
348 #define NET_GPMC_CONFIG4 0x1c091c09
349 #define NET_GPMC_CONFIG5 0x04181f1f
350 #define NET_GPMC_CONFIG6 0x00000FCF
351 #define NET_GPMC_CONFIG7 0x00000f6c
353 /* max number of GPMC Chip Selects */
354 #define GPMC_MAX_CS 8
355 /* max number of GPMC regs */
356 #define GPMC_MAX_REG 7
359 #define PISMO1_NAND 2
362 #define PISMO1_ONENAND 5
364 #define PISMO2_NAND_CS0 7
365 #define PISMO2_NAND_CS1 8
367 /* make it readable for the gpmc_init */
368 #define PISMO1_NOR_BASE FLASH_BASE
369 #define PISMO1_NAND_BASE NAND_BASE
370 #define PISMO2_CS0_BASE PISMO2_MAP1
371 #define PISMO1_ONEN_BASE ONENAND_MAP
372 #define DBG_MPDB_BASE DEBUG_BASE
376 /* Function prototypes */
379 u32 is_mem_sdr(void);
382 u32 get_sdr_cs_size(u32);
383 u32 get_sdr_cs_offset(u32);
385 #endif /* __ASSEMBLY__ */
387 #endif /* endif _MEM_H_ */