arch/arm/include/asm/arch-omap3/dss.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  * Syed Mohammed Khasim <khasim@ti.com>
   5  *
   6  * Referred to Linux Kernel DSS driver files for OMAP3 by
   7  * Tomi Valkeinen from drivers/video/omap2/dss/
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation's version 2 and any
  15  * later version the License.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef DSS_H
  29 #define DSS_H
  30
  31 /*
  32  * DSS Base Registers
  33  */
  34 #define OMAP3_DSS_BASE          0x48050000
  35 #define OMAP3_DISPC_BASE        0x48050400
  36 #define OMAP3_VENC_BASE         0x48050C00
  37
  38 /* DSS Registers */
  39 struct dss_regs {
  40         u32 revision;                           /* 0x00 */
  41         u8 res1[12];                            /* 0x04 */
  42         u32 sysconfig;                          /* 0x10 */
  43         u32 sysstatus;                          /* 0x14 */
  44         u32 irqstatus;                          /* 0x18 */
  45         u8 res2[36];                            /* 0x1C */
  46         u32 control;                            /* 0x40 */
  47         u32 sdi_control;                        /* 0x44 */
  48         u32 pll_control;                        /* 0x48 */
  49 };
  50
  51 /* DISPC Registers */
  52 struct dispc_regs {
  53         u32 revision;                           /* 0x00 */
  54         u8 res1[12];                            /* 0x04 */
  55         u32 sysconfig;                          /* 0x10 */
  56         u32 sysstatus;                          /* 0x14 */
  57         u32 irqstatus;                          /* 0x18 */
  58         u32 irqenable;                          /* 0x1C */
  59         u8 res2[32];                            /* 0x20 */
  60         u32 control;                            /* 0x40 */
  61         u32 config;                             /* 0x44 */
  62         u32 reserve_2;                          /* 0x48 */
  63         u32 default_color0;                     /* 0x4C */
  64         u32 default_color1;                     /* 0x50 */
  65         u32 trans_color0;                       /* 0x54 */
  66         u32 trans_color1;                       /* 0x58 */
  67         u32 line_status;                        /* 0x5C */
  68         u32 line_number;                        /* 0x60 */
  69         u32 timing_h;                           /* 0x64 */
  70         u32 timing_v;                           /* 0x68 */
  71         u32 pol_freq;                           /* 0x6C */
  72         u32 divisor;                            /* 0x70 */
  73         u32 global_alpha;                       /* 0x74 */
  74         u32 size_dig;                           /* 0x78 */
  75         u32 size_lcd;                           /* 0x7C */
  76         u32 gfx_ba0;                            /* 0x80 */
  77         u32 gfx_ba1;                            /* 0x84 */
  78         u32 gfx_position;                       /* 0x88 */
  79         u32 gfx_size;                           /* 0x8C */
  80         u8 unused[16];                          /* 0x90 */
  81         u32 gfx_attributes;                     /* 0xA0 */
  82         u32 gfx_fifo_threshold;                 /* 0xA4 */
  83         u32 gfx_fifo_size_status;               /* 0xA8 */
  84         u32 gfx_row_inc;                        /* 0xAC */
  85         u32 gfx_pixel_inc;                      /* 0xB0 */
  86         u32 gfx_window_skip;                    /* 0xB4 */
  87         u32 gfx_table_ba;                       /* 0xB8 */
  88 };
  89
  90 /* VENC Registers */
  91 struct venc_regs {
  92         u32 rev_id;                             /* 0x00 */
  93         u32 status;                             /* 0x04 */
  94         u32 f_control;                          /* 0x08 */
  95         u32 reserve_1;                          /* 0x0C */
  96         u32 vidout_ctrl;                        /* 0x10 */
  97         u32 sync_ctrl;                          /* 0x14 */
  98         u32 reserve_2;                          /* 0x18 */
  99         u32 llen;                               /* 0x1C */
 100         u32 flens;                              /* 0x20 */
 101         u32 hfltr_ctrl;                         /* 0x24 */
 102         u32 cc_carr_wss_carr;                   /* 0x28 */
 103         u32 c_phase;                            /* 0x2C */
 104         u32 gain_u;                             /* 0x30 */
 105         u32 gain_v;                             /* 0x34 */
 106         u32 gain_y;                             /* 0x38 */
 107         u32 black_level;                        /* 0x3C */
 108         u32 blank_level;                        /* 0x40 */
 109         u32 x_color;                            /* 0x44 */
 110         u32 m_control;                          /* 0x48 */
 111         u32 bstamp_wss_data;                    /* 0x4C */
 112         u32 s_carr;                             /* 0x50 */
 113         u32 line21;                             /* 0x54 */
 114         u32 ln_sel;                             /* 0x58 */
 115         u32 l21__wc_ctl;                        /* 0x5C */
 116         u32 htrigger_vtrigger;                  /* 0x60 */
 117         u32 savid__eavid;                       /* 0x64 */
 118         u32 flen__fal;                          /* 0x68 */
 119         u32 lal__phase_reset;                   /* 0x6C */
 120         u32 hs_int_start_stop_x;                /* 0x70 */
 121         u32 hs_ext_start_stop_x;                /* 0x74 */
 122         u32 vs_int_start_x;                     /* 0x78 */
 123         u32 vs_int_stop_x__vs_int_start_y;      /* 0x7C */
 124         u32 vs_int_stop_y__vs_ext_start_x;      /* 0x80 */
 125         u32 vs_ext_stop_x__vs_ext_start_y;      /* 0x84 */
 126         u32 vs_ext_stop_y;                      /* 0x88 */
 127         u32 reserve_3;                          /* 0x8C */
 128         u32 avid_start_stop_x;                  /* 0x90 */
 129         u32 avid_start_stop_y;                  /* 0x94 */
 130         u32 reserve_4;                          /* 0x98 */
 131         u32 reserve_5;                          /* 0x9C */
 132         u32 fid_int_start_x__fid_int_start_y;   /* 0xA0 */
 133         u32 fid_int_offset_y__fid_ext_start_x;  /* 0xA4 */
 134         u32 fid_ext_start_y__fid_ext_offset_y;  /* 0xA8 */
 135         u32 reserve_6;                          /* 0xAC */
 136         u32 tvdetgp_int_start_stop_x;           /* 0xB0 */
 137         u32 tvdetgp_int_start_stop_y;           /* 0xB4 */
 138         u32 gen_ctrl;                           /* 0xB8 */
 139         u32 reserve_7;                          /* 0xBC */
 140         u32 reserve_8;                          /* 0xC0 */
 141         u32 output_control;                     /* 0xC4 */
 142         u32 dac_b__dac_c;                       /* 0xC8 */
 143         u32 height_width;                       /* 0xCC */
 144 };
 145
 146 /* Few Register Offsets */
 147 #define FRAME_MODE_SHIFT                        1
 148 #define TFTSTN_SHIFT                            3
 149 #define DATALINES_SHIFT                         8
 150
 151 #define GFX_ENABLE                              1
 152 #define GFX_FORMAT_SHIFT                        1
 153 #define LOADMODE_SHIFT                          1
 154
 155 #define DSS_SOFTRESET                           (1 << 1)
 156 #define DSS_RESETDONE                           1
 157
 158 /* Enabling Display controller */
 159 #define LCD_ENABLE                              1
 160 #define DIG_ENABLE                              (1 << 1)
 161 #define GO_LCD                                  (1 << 5)
 162 #define GO_DIG                                  (1 << 6)
 163 #define GP_OUT0                                 (1 << 15)
 164 #define GP_OUT1                                 (1 << 16)
 165
 166 #define DISPC_ENABLE                            (LCD_ENABLE | \
 167                                                  DIG_ENABLE | \
 168                                                  GO_LCD | \
 169                                                  GO_DIG | \
 170                                                  GP_OUT0| \
 171                                                  GP_OUT1)
 172
 173 /* Configure VENC DSS Params */
 174 #define VENC_CLK_ENABLE                         (1 << 3)
 175 #define DAC_DEMEN                               (1 << 4)
 176 #define DAC_POWERDN                             (1 << 5)
 177 #define VENC_OUT_SEL                            (1 << 6)
 178 #define DIG_LPP_SHIFT                           16
 179 #define VENC_DSS_CONFIG                         (VENC_CLK_ENABLE | \
 180                                                  DAC_DEMEN | \
 181                                                  DAC_POWERDN | \
 182                                                  VENC_OUT_SEL)
 183 /*
 184  * Panel Configuration
 185  */
 186 struct panel_config {
 187         u32 timing_h;
 188         u32 timing_v;
 189         u32 pol_freq;
 190         u32 divisor;
 191         u32 lcd_size;
 192         u32 panel_type;
 193         u32 data_lines;
 194         u32 load_mode;
 195         u32 panel_color;
 196         void *frame_buffer;
 197 };
 198
 199 /*
 200  * Generic DSS Functions
 201  */
 202 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
 203                         u32 height, u32 width);
 204 void omap3_dss_panel_config(const struct panel_config *panel_cfg);
 205 void omap3_dss_enable(void);
 206
 207 #endif /* DSS_H */