2 * am35x_def.h - TI's AM35x specific definitions.
4 * Based on arch/arm/include/asm/arch-omap3/cpu.h
6 * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
8 * Copyright (c) 2010 Texas Instruments Incorporated
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
29 #include <asm/types.h>
30 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
32 #ifndef __KERNEL_STRICT_NAMES
35 /* LVL_INTR_CLEAR bits */
36 #define USBOTGSS_INT_CLR (1 << 4)
38 /* IP_SW_RESET bits */
39 #define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */
40 #define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */
43 #define CONF2_PHY_GPIOMODE (1 << 23)
44 #define CONF2_OTGMODE (3 << 14)
45 #define CONF2_NO_OVERRIDE (0 << 14)
46 #define CONF2_FORCE_HOST (1 << 14)
47 #define CONF2_FORCE_DEVICE (2 << 14)
48 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
49 #define CONF2_SESENDEN (1 << 13)
50 #define CONF2_VBDTCTEN (1 << 12)
51 #define CONF2_REFFREQ_24MHZ (2 << 8)
52 #define CONF2_REFFREQ_26MHZ (7 << 8)
53 #define CONF2_REFFREQ_13MHZ (6 << 8)
54 #define CONF2_REFFREQ (0xf << 8)
55 #define CONF2_PHYCLKGD (1 << 7)
56 #define CONF2_VBUSSENSE (1 << 6)
57 #define CONF2_PHY_PLLON (1 << 5)
58 #define CONF2_RESET (1 << 4)
59 #define CONF2_PHYPWRDN (1 << 3)
60 #define CONF2_OTGPWRDN (1 << 2)
61 #define CONF2_DATPOL (1 << 1)
63 /* General register mappings of system control module */
64 #define AM35X_SCM_GEN_BASE 0x48002270
65 struct am35x_scm_general {
66 u32 res1[0xC4]; /* 0x000 - 0x30C */
67 u32 devconf2; /* 0x310 */
68 u32 devconf3; /* 0x314 */
69 u32 res2[0x2]; /* 0x318 - 0x31C */
70 u32 cba_priority; /* 0x320 */
71 u32 lvl_intr_clr; /* 0x324 */
72 u32 ip_sw_reset; /* 0x328 */
73 u32 ipss_clk_ctrl; /* 0x32C */
75 #define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
77 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
79 #endif /*__ASSEMBLY__ */
80 #endif /* __KERNEL_STRICT_NAMES */
82 #endif /* _AM35X_DEF_H_ */