arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Freescale i.MX28 CLKCTRL Register Definitions
   4  *
   5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   6  * on behalf of DENX Software Engineering GmbH
   7  *
   8  * Based on code from LTIB:
   9  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  10  */
  11
  12 #ifndef __MX28_REGS_CLKCTRL_H__
  13 #define __MX28_REGS_CLKCTRL_H__
  14
  15 #include <asm/mach-imx/regs-common.h>
  16
  17 #ifndef __ASSEMBLY__
  18 struct mxs_clkctrl_regs {
  19         mxs_reg_32(hw_clkctrl_pll0ctrl0)        /* 0x00 */
  20         uint32_t        hw_clkctrl_pll0ctrl1;   /* 0x10 */
  21         uint32_t        reserved_pll0ctrl1[3];  /* 0x14-0x1c */
  22         mxs_reg_32(hw_clkctrl_pll1ctrl0)        /* 0x20 */
  23         uint32_t        hw_clkctrl_pll1ctrl1;   /* 0x30 */
  24         uint32_t        reserved_pll1ctrl1[3];  /* 0x34-0x3c */
  25         mxs_reg_32(hw_clkctrl_pll2ctrl0)        /* 0x40 */
  26         mxs_reg_32(hw_clkctrl_cpu)              /* 0x50 */
  27         mxs_reg_32(hw_clkctrl_hbus)             /* 0x60 */
  28         mxs_reg_32(hw_clkctrl_xbus)             /* 0x70 */
  29         mxs_reg_32(hw_clkctrl_xtal)             /* 0x80 */
  30         uint32_t        hw_clkctrl_ssp0;        /* 0x90 */
  31         uint32_t        reserved_ssp0[3];       /* 0x94-0x9c */
  32         uint32_t        hw_clkctrl_ssp1;        /* 0xa0 */
  33         uint32_t        reserved_ssp1[3];       /* 0xa4-0xac */
  34         uint32_t        hw_clkctrl_ssp2;        /* 0xb0 */
  35         uint32_t        reserved_ssp2[3];       /* 0xb4-0xbc */
  36         uint32_t        hw_clkctrl_ssp3;        /* 0xc0 */
  37         uint32_t        reserved_ssp3[3];       /* 0xc4-0xcc */
  38         uint32_t        hw_clkctrl_gpmi;        /* 0xd0 */
  39         uint32_t        reserved_gpmi[3];       /* 0xd4-0xdc */
  40         mxs_reg_32(hw_clkctrl_spdif)            /* 0xe0 */
  41         mxs_reg_32(hw_clkctrl_emi)              /* 0xf0 */
  42         mxs_reg_32(hw_clkctrl_saif0)            /* 0x100 */
  43         mxs_reg_32(hw_clkctrl_saif1)            /* 0x110 */
  44         mxs_reg_32(hw_clkctrl_lcdif)            /* 0x120 */
  45         mxs_reg_32(hw_clkctrl_etm)              /* 0x130 */
  46         mxs_reg_32(hw_clkctrl_enet)             /* 0x140 */
  47         mxs_reg_32(hw_clkctrl_hsadc)            /* 0x150 */
  48         mxs_reg_32(hw_clkctrl_flexcan)          /* 0x160 */
  49
  50         uint32_t        reserved[16];
  51
  52         mxs_reg_8(hw_clkctrl_frac0)             /* 0x1b0 */
  53         mxs_reg_8(hw_clkctrl_frac1)             /* 0x1c0 */
  54         mxs_reg_32(hw_clkctrl_clkseq)           /* 0x1d0 */
  55         mxs_reg_32(hw_clkctrl_reset)            /* 0x1e0 */
  56         mxs_reg_32(hw_clkctrl_status)           /* 0x1f0 */
  57         mxs_reg_32(hw_clkctrl_version)          /* 0x200 */
  58 };
  59 #endif
  60
  61 #define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK          (0x3 << 28)
  62 #define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET        28
  63 #define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT       (0x0 << 28)
  64 #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2       (0x1 << 28)
  65 #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05      (0x2 << 28)
  66 #define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED     (0x3 << 28)
  67 #define CLKCTRL_PLL0CTRL0_CP_SEL_MASK           (0x3 << 24)
  68 #define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET         24
  69 #define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT        (0x0 << 24)
  70 #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2        (0x1 << 24)
  71 #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05       (0x2 << 24)
  72 #define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED      (0x3 << 24)
  73 #define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK          (0x3 << 20)
  74 #define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET        20
  75 #define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT       (0x0 << 20)
  76 #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER         (0x1 << 20)
  77 #define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST        (0x2 << 20)
  78 #define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED     (0x3 << 20)
  79 #define CLKCTRL_PLL0CTRL0_EN_USB_CLKS           (1 << 18)
  80 #define CLKCTRL_PLL0CTRL0_POWER                 (1 << 17)
  81
  82 #define CLKCTRL_PLL0CTRL1_LOCK                  (1 << 31)
  83 #define CLKCTRL_PLL0CTRL1_FORCE_LOCK            (1 << 30)
  84 #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK       0xffff
  85 #define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET     0
  86
  87 #define CLKCTRL_PLL1CTRL0_CLKGATEEMI            (1 << 31)
  88 #define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK          (0x3 << 28)
  89 #define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET        28
  90 #define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT       (0x0 << 28)
  91 #define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2       (0x1 << 28)
  92 #define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05      (0x2 << 28)
  93 #define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED     (0x3 << 28)
  94 #define CLKCTRL_PLL1CTRL0_CP_SEL_MASK           (0x3 << 24)
  95 #define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET         24
  96 #define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT        (0x0 << 24)
  97 #define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2        (0x1 << 24)
  98 #define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05       (0x2 << 24)
  99 #define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED      (0x3 << 24)
 100 #define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK          (0x3 << 20)
 101 #define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET        20
 102 #define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT       (0x0 << 20)
 103 #define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER         (0x1 << 20)
 104 #define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST        (0x2 << 20)
 105 #define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED     (0x3 << 20)
 106 #define CLKCTRL_PLL1CTRL0_EN_USB_CLKS           (1 << 18)
 107 #define CLKCTRL_PLL1CTRL0_POWER                 (1 << 17)
 108
 109 #define CLKCTRL_PLL1CTRL1_LOCK                  (1 << 31)
 110 #define CLKCTRL_PLL1CTRL1_FORCE_LOCK            (1 << 30)
 111 #define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK       0xffff
 112 #define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET     0
 113
 114 #define CLKCTRL_PLL2CTRL0_CLKGATE               (1 << 31)
 115 #define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK          (0x3 << 28)
 116 #define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET        28
 117 #define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B       (1 << 26)
 118 #define CLKCTRL_PLL2CTRL0_CP_SEL_MASK           (0x3 << 24)
 119 #define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET         24
 120 #define CLKCTRL_PLL2CTRL0_POWER                 (1 << 23)
 121
 122 #define CLKCTRL_CPU_BUSY_REF_XTAL               (1 << 29)
 123 #define CLKCTRL_CPU_BUSY_REF_CPU                (1 << 28)
 124 #define CLKCTRL_CPU_DIV_XTAL_FRAC_EN            (1 << 26)
 125 #define CLKCTRL_CPU_DIV_XTAL_MASK               (0x3ff << 16)
 126 #define CLKCTRL_CPU_DIV_XTAL_OFFSET             16
 127 #define CLKCTRL_CPU_INTERRUPT_WAIT              (1 << 12)
 128 #define CLKCTRL_CPU_DIV_CPU_FRAC_EN             (1 << 10)
 129 #define CLKCTRL_CPU_DIV_CPU_MASK                0x3f
 130 #define CLKCTRL_CPU_DIV_CPU_OFFSET              0
 131
 132 #define CLKCTRL_HBUS_ASM_BUSY                   (1 << 31)
 133 #define CLKCTRL_HBUS_DCP_AS_ENABLE              (1 << 30)
 134 #define CLKCTRL_HBUS_PXP_AS_ENABLE              (1 << 29)
 135 #define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE      (1 << 27)
 136 #define CLKCTRL_HBUS_APBHDMA_AS_ENABLE          (1 << 26)
 137 #define CLKCTRL_HBUS_APBXDMA_AS_ENABLE          (1 << 25)
 138 #define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE      (1 << 24)
 139 #define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE          (1 << 23)
 140 #define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE         (1 << 22)
 141 #define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE        (1 << 21)
 142 #define CLKCTRL_HBUS_ASM_ENABLE                 (1 << 20)
 143 #define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE      (1 << 19)
 144 #define CLKCTRL_HBUS_SLOW_DIV_MASK              (0x7 << 16)
 145 #define CLKCTRL_HBUS_SLOW_DIV_OFFSET            16
 146 #define CLKCTRL_HBUS_SLOW_DIV_BY1               (0x0 << 16)
 147 #define CLKCTRL_HBUS_SLOW_DIV_BY2               (0x1 << 16)
 148 #define CLKCTRL_HBUS_SLOW_DIV_BY4               (0x2 << 16)
 149 #define CLKCTRL_HBUS_SLOW_DIV_BY8               (0x3 << 16)
 150 #define CLKCTRL_HBUS_SLOW_DIV_BY16              (0x4 << 16)
 151 #define CLKCTRL_HBUS_SLOW_DIV_BY32              (0x5 << 16)
 152 #define CLKCTRL_HBUS_DIV_FRAC_EN                (1 << 5)
 153 #define CLKCTRL_HBUS_DIV_MASK                   0x1f
 154 #define CLKCTRL_HBUS_DIV_OFFSET                 0
 155
 156 #define CLKCTRL_XBUS_BUSY                       (1 << 31)
 157 #define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE      (1 << 11)
 158 #define CLKCTRL_XBUS_DIV_FRAC_EN                (1 << 10)
 159 #define CLKCTRL_XBUS_DIV_MASK                   0x3ff
 160 #define CLKCTRL_XBUS_DIV_OFFSET                 0
 161
 162 #define CLKCTRL_XTAL_UART_CLK_GATE              (1 << 31)
 163 #define CLKCTRL_XTAL_PWM_CLK24M_GATE            (1 << 29)
 164 #define CLKCTRL_XTAL_TIMROT_CLK32K_GATE         (1 << 26)
 165 #define CLKCTRL_XTAL_DIV_UART_MASK              0x3
 166 #define CLKCTRL_XTAL_DIV_UART_OFFSET            0
 167
 168 #define CLKCTRL_SSP_CLKGATE                     (1 << 31)
 169 #define CLKCTRL_SSP_BUSY                        (1 << 29)
 170 #define CLKCTRL_SSP_DIV_FRAC_EN                 (1 << 9)
 171 #define CLKCTRL_SSP_DIV_MASK                    0x1ff
 172 #define CLKCTRL_SSP_DIV_OFFSET                  0
 173
 174 #define CLKCTRL_GPMI_CLKGATE                    (1 << 31)
 175 #define CLKCTRL_GPMI_BUSY                       (1 << 29)
 176 #define CLKCTRL_GPMI_DIV_FRAC_EN                (1 << 10)
 177 #define CLKCTRL_GPMI_DIV_MASK                   0x3ff
 178 #define CLKCTRL_GPMI_DIV_OFFSET                 0
 179
 180 #define CLKCTRL_SPDIF_CLKGATE                   (1 << 31)
 181
 182 #define CLKCTRL_EMI_CLKGATE                     (1 << 31)
 183 #define CLKCTRL_EMI_SYNC_MODE_EN                (1 << 30)
 184 #define CLKCTRL_EMI_BUSY_REF_XTAL               (1 << 29)
 185 #define CLKCTRL_EMI_BUSY_REF_EMI                (1 << 28)
 186 #define CLKCTRL_EMI_BUSY_REF_CPU                (1 << 27)
 187 #define CLKCTRL_EMI_BUSY_SYNC_MODE              (1 << 26)
 188 #define CLKCTRL_EMI_BUSY_DCC_RESYNC             (1 << 17)
 189 #define CLKCTRL_EMI_DCC_RESYNC_ENABLE           (1 << 16)
 190 #define CLKCTRL_EMI_DIV_XTAL_MASK               (0xf << 8)
 191 #define CLKCTRL_EMI_DIV_XTAL_OFFSET             8
 192 #define CLKCTRL_EMI_DIV_EMI_MASK                0x3f
 193 #define CLKCTRL_EMI_DIV_EMI_OFFSET              0
 194
 195 #define CLKCTRL_SAIF0_CLKGATE                   (1 << 31)
 196 #define CLKCTRL_SAIF0_BUSY                      (1 << 29)
 197 #define CLKCTRL_SAIF0_DIV_FRAC_EN               (1 << 16)
 198 #define CLKCTRL_SAIF0_DIV_MASK                  0xffff
 199 #define CLKCTRL_SAIF0_DIV_OFFSET                0
 200
 201 #define CLKCTRL_SAIF1_CLKGATE                   (1 << 31)
 202 #define CLKCTRL_SAIF1_BUSY                      (1 << 29)
 203 #define CLKCTRL_SAIF1_DIV_FRAC_EN               (1 << 16)
 204 #define CLKCTRL_SAIF1_DIV_MASK                  0xffff
 205 #define CLKCTRL_SAIF1_DIV_OFFSET                0
 206
 207 #define CLKCTRL_DIS_LCDIF_CLKGATE               (1 << 31)
 208 #define CLKCTRL_DIS_LCDIF_BUSY                  (1 << 29)
 209 #define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN           (1 << 13)
 210 #define CLKCTRL_DIS_LCDIF_DIV_MASK              0x1fff
 211 #define CLKCTRL_DIS_LCDIF_DIV_OFFSET            0
 212
 213 #define CLKCTRL_ETM_CLKGATE                     (1 << 31)
 214 #define CLKCTRL_ETM_BUSY                        (1 << 29)
 215 #define CLKCTRL_ETM_DIV_FRAC_EN                 (1 << 7)
 216 #define CLKCTRL_ETM_DIV_MASK                    0x7f
 217 #define CLKCTRL_ETM_DIV_OFFSET                  0
 218
 219 #define CLKCTRL_ENET_SLEEP                      (1 << 31)
 220 #define CLKCTRL_ENET_DISABLE                    (1 << 30)
 221 #define CLKCTRL_ENET_STATUS                     (1 << 29)
 222 #define CLKCTRL_ENET_BUSY_TIME                  (1 << 27)
 223 #define CLKCTRL_ENET_DIV_TIME_MASK              (0x3f << 21)
 224 #define CLKCTRL_ENET_DIV_TIME_OFFSET            21
 225 #define CLKCTRL_ENET_TIME_SEL_MASK              (0x3 << 19)
 226 #define CLKCTRL_ENET_TIME_SEL_OFFSET            19
 227 #define CLKCTRL_ENET_TIME_SEL_XTAL              (0x0 << 19)
 228 #define CLKCTRL_ENET_TIME_SEL_PLL               (0x1 << 19)
 229 #define CLKCTRL_ENET_TIME_SEL_RMII_CLK          (0x2 << 19)
 230 #define CLKCTRL_ENET_TIME_SEL_UNDEFINED         (0x3 << 19)
 231 #define CLKCTRL_ENET_CLK_OUT_EN                 (1 << 18)
 232 #define CLKCTRL_ENET_RESET_BY_SW_CHIP           (1 << 17)
 233 #define CLKCTRL_ENET_RESET_BY_SW                (1 << 16)
 234
 235 #define CLKCTRL_HSADC_RESETB                    (1 << 30)
 236 #define CLKCTRL_HSADC_FREQDIV_MASK              (0x3 << 28)
 237 #define CLKCTRL_HSADC_FREQDIV_OFFSET            28
 238
 239 #define CLKCTRL_FLEXCAN_STOP_CAN0               (1 << 30)
 240 #define CLKCTRL_FLEXCAN_CAN0_STATUS             (1 << 29)
 241 #define CLKCTRL_FLEXCAN_STOP_CAN1               (1 << 28)
 242 #define CLKCTRL_FLEXCAN_CAN1_STATUS             (1 << 27)
 243
 244 #define CLKCTRL_FRAC_CLKGATE                    (1 << 7)
 245 #define CLKCTRL_FRAC_STABLE                     (1 << 6)
 246 #define CLKCTRL_FRAC_FRAC_MASK                  0x3f
 247 #define CLKCTRL_FRAC_FRAC_OFFSET                0
 248 #define CLKCTRL_FRAC0_CPU                       0
 249 #define CLKCTRL_FRAC0_EMI                       1
 250 #define CLKCTRL_FRAC0_IO1                       2
 251 #define CLKCTRL_FRAC0_IO0                       3
 252 #define CLKCTRL_FRAC1_PIX                       0
 253 #define CLKCTRL_FRAC1_HSADC                     1
 254 #define CLKCTRL_FRAC1_GPMI                      2
 255
 256 #define CLKCTRL_CLKSEQ_BYPASS_CPU               (1 << 18)
 257 #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF         (1 << 14)
 258 #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS  (0x1 << 14)
 259 #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD     (0x0 << 14)
 260 #define CLKCTRL_CLKSEQ_BYPASS_ETM               (1 << 8)
 261 #define CLKCTRL_CLKSEQ_BYPASS_EMI               (1 << 7)
 262 #define CLKCTRL_CLKSEQ_BYPASS_SSP3              (1 << 6)
 263 #define CLKCTRL_CLKSEQ_BYPASS_SSP2              (1 << 5)
 264 #define CLKCTRL_CLKSEQ_BYPASS_SSP1              (1 << 4)
 265 #define CLKCTRL_CLKSEQ_BYPASS_SSP0              (1 << 3)
 266 #define CLKCTRL_CLKSEQ_BYPASS_GPMI              (1 << 2)
 267 #define CLKCTRL_CLKSEQ_BYPASS_SAIF1             (1 << 1)
 268 #define CLKCTRL_CLKSEQ_BYPASS_SAIF0             (1 << 0)
 269
 270 #define CLKCTRL_RESET_WDOG_POR_DISABLE          (1 << 5)
 271 #define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE     (1 << 4)
 272 #define CLKCTRL_RESET_THERMAL_RESET_ENABLE      (1 << 3)
 273 #define CLKCTRL_RESET_THERMAL_RESET_DEFAULT     (1 << 2)
 274 #define CLKCTRL_RESET_CHIP                      (1 << 1)
 275 #define CLKCTRL_RESET_DIG                       (1 << 0)
 276
 277 #define CLKCTRL_STATUS_CPU_LIMIT_MASK           (0x3 << 30)
 278 #define CLKCTRL_STATUS_CPU_LIMIT_OFFSET         30
 279
 280 #define CLKCTRL_VERSION_MAJOR_MASK              (0xff << 24)
 281 #define CLKCTRL_VERSION_MAJOR_OFFSET            24
 282 #define CLKCTRL_VERSION_MINOR_MASK              (0xff << 16)
 283 #define CLKCTRL_VERSION_MINOR_OFFSET            16
 284 #define CLKCTRL_VERSION_STEP_MASK               0xffff
 285 #define CLKCTRL_VERSION_STEP_OFFSET             0
 286
 287 #endif /* __MX28_REGS_CLKCTRL_H__ */