arch/arm/include/asm/arch-mx7ulp/pcc.h

   1 /*
   2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _ASM_ARCH_PCC_H
   8 #define _ASM_ARCH_PCC_H
   9
  10 #include <common.h>
  11 #include <asm/arch/scg.h>
  12
  13 /* PCC2 */
  14
  15 enum pcc2_entry {
  16         /* On-Platform (32 entries) */
  17         RSVD0_PCC2_SLOT                 = 0,
  18         RSVD1_PCC2_SLOT                 = 1,
  19         CA7_GIC_PCC2_SLOT               = 2,
  20         RSVD3_PCC2_SLOT                 = 3,
  21         RSVD4_PCC2_SLOT                 = 4,
  22         RSVD5_PCC2_SLOT                 = 5,
  23         RSVD6_PCC2_SLOT                 = 6,
  24         RSVD7_PCC2_SLOT                 = 7,
  25         DMA1_PCC2_SLOT                  = 8,
  26         RSVD9_PCC2_SLOT                 = 9,
  27         RSVD10_PCC2_SLOT                = 10,
  28         RSVD11_PCC2_SLOT                = 11,
  29         RSVD12_PCC2_SLOT                = 12,
  30         RSVD13_PCC2_SLOT                = 13,
  31         RSVD14_PCC2_SLOT                = 14,
  32         RGPIO1_PCC2_SLOT                = 15,
  33         FLEXBUS0_PCC2_SLOT              = 16,
  34         RSVD17_PCC2_SLOT                = 17,
  35         RSVD18_PCC2_SLOT                = 18,
  36         RSVD19_PCC2_SLOT                = 19,
  37         RSVD20_PCC2_SLOT                = 20,
  38         RSVD21_PCC2_SLOT                = 21,
  39         RSVD22_PCC2_SLOT                = 22,
  40         RSVD23_PCC2_SLOT                = 23,
  41         RSVD24_PCC2_SLOT                = 24,
  42         RSVD25_PCC2_SLOT                = 25,
  43         RSVD26_PCC2_SLOT                = 26,
  44         SEMA42_1_PCC2_SLOT              = 27,
  45         RSVD28_PCC2_SLOT                = 28,
  46         RSVD29_PCC2_SLOT                = 29,
  47         RSVD30_PCC2_SLOT                = 30,
  48         RSVD31_PCC2_SLOT                = 31,
  49
  50         /* Off-Platform (96 entries) */
  51         RSVD32_PCC2_SLOT                = 32,
  52         DMA1_CH_MUX0_PCC2_SLOT          = 33,
  53         MU_B_PCC2_SLOT                  = 34,
  54         SNVS_PCC2_SLOT                  = 35,
  55         CAAM_PCC2_SLOT                  = 36,
  56         LPTPM4_PCC2_SLOT                = 37,
  57         LPTPM5_PCC2_SLOT                = 38,
  58         LPIT1_PCC2_SLOT                 = 39,
  59         RSVD40_PCC2_SLOT                = 40,
  60         LPSPI2_PCC2_SLOT                = 41,
  61         LPSPI3_PCC2_SLOT                = 42,
  62         LPI2C4_PCC2_SLOT                = 43,
  63         LPI2C5_PCC2_SLOT                = 44,
  64         LPUART4_PCC2_SLOT               = 45,
  65         LPUART5_PCC2_SLOT               = 46,
  66         RSVD47_PCC2_SLOT                = 47,
  67         RSVD48_PCC2_SLOT                = 48,
  68         FLEXIO1_PCC2_SLOT               = 49,
  69         RSVD50_PCC2_SLOT                = 50,
  70         USBOTG0_PCC2_SLOT               = 51,
  71         USBOTG1_PCC2_SLOT               = 52,
  72         USBPHY_PCC2_SLOT                = 53,
  73         USB_PL301_PCC2_SLOT             = 54,
  74         USDHC0_PCC2_SLOT                = 55,
  75         USDHC1_PCC2_SLOT                = 56,
  76         RSVD57_PCC2_SLOT                = 57,
  77         TRGMUX1_PCC2_SLOT               = 58,
  78         RSVD59_PCC2_SLOT                = 59,
  79         RSVD60_PCC2_SLOT                = 60,
  80         WDG1_PCC2_SLOT                  = 61,
  81         SCG1_PCC2_SLOT                  = 62,
  82         PCC2_PCC2_SLOT                  = 63,
  83         PMC1_PCC2_SLOT                  = 64,
  84         SMC1_PCC2_SLOT                  = 65,
  85         RCM1_PCC2_SLOT                  = 66,
  86         WDG2_PCC2_SLOT                  = 67,
  87         RSVD68_PCC2_SLOT                = 68,
  88         TEST_SPACE1_PCC2_SLOT           = 69,
  89         TEST_SPACE2_PCC2_SLOT           = 70,
  90         TEST_SPACE3_PCC2_SLOT           = 71,
  91         RSVD72_PCC2_SLOT                = 72,
  92         RSVD73_PCC2_SLOT                = 73,
  93         RSVD74_PCC2_SLOT                = 74,
  94         RSVD75_PCC2_SLOT                = 75,
  95         RSVD76_PCC2_SLOT                = 76,
  96         RSVD77_PCC2_SLOT                = 77,
  97         RSVD78_PCC2_SLOT                = 78,
  98         RSVD79_PCC2_SLOT                = 79,
  99         RSVD80_PCC2_SLOT                = 80,
 100         RSVD81_PCC2_SLOT                = 81,
 101         RSVD82_PCC2_SLOT                = 82,
 102         RSVD83_PCC2_SLOT                = 83,
 103         RSVD84_PCC2_SLOT                = 84,
 104         RSVD85_PCC2_SLOT                = 85,
 105         RSVD86_PCC2_SLOT                = 86,
 106         RSVD87_PCC2_SLOT                = 87,
 107         RSVD88_PCC2_SLOT                = 88,
 108         RSVD89_PCC2_SLOT                = 89,
 109         RSVD90_PCC2_SLOT                = 90,
 110         RSVD91_PCC2_SLOT                = 91,
 111         RSVD92_PCC2_SLOT                = 92,
 112         RSVD93_PCC2_SLOT                = 93,
 113         RSVD94_PCC2_SLOT                = 94,
 114         RSVD95_PCC2_SLOT                = 95,
 115         RSVD96_PCC2_SLOT                = 96,
 116         RSVD97_PCC2_SLOT                = 97,
 117         RSVD98_PCC2_SLOT                = 98,
 118         RSVD99_PCC2_SLOT                = 99,
 119         RSVD100_PCC2_SLOT               = 100,
 120         RSVD101_PCC2_SLOT               = 101,
 121         RSVD102_PCC2_SLOT               = 102,
 122         RSVD103_PCC2_SLOT               = 103,
 123         RSVD104_PCC2_SLOT               = 104,
 124         RSVD105_PCC2_SLOT               = 105,
 125         RSVD106_PCC2_SLOT               = 106,
 126         RSVD107_PCC2_SLOT               = 107,
 127         RSVD108_PCC2_SLOT               = 108,
 128         RSVD109_PCC2_SLOT               = 109,
 129         RSVD110_PCC2_SLOT               = 110,
 130         RSVD111_PCC2_SLOT               = 111,
 131         RSVD112_PCC2_SLOT               = 112,
 132         RSVD113_PCC2_SLOT               = 113,
 133         RSVD114_PCC2_SLOT               = 114,
 134         RSVD115_PCC2_SLOT               = 115,
 135         RSVD116_PCC2_SLOT               = 116,
 136         RSVD117_PCC2_SLOT               = 117,
 137         RSVD118_PCC2_SLOT               = 118,
 138         RSVD119_PCC2_SLOT               = 119,
 139         RSVD120_PCC2_SLOT               = 120,
 140         RSVD121_PCC2_SLOT               = 121,
 141         RSVD122_PCC2_SLOT               = 122,
 142         RSVD123_PCC2_SLOT               = 123,
 143         RSVD124_PCC2_SLOT               = 124,
 144         RSVD125_PCC2_SLOT               = 125,
 145         RSVD126_PCC2_SLOT               = 126,
 146         RSVD127_PCC2_SLOT               = 127,
 147 };
 148
 149 enum pcc3_entry {
 150         /* On-Platform (32 entries) */
 151         RSVD0_PCC3_SLOT                 = 0,
 152         RSVD1_PCC3_SLOT                 = 1,
 153         RSVD2_PCC3_SLOT                 = 2,
 154         RSVD3_PCC3_SLOT                 = 3,
 155         RSVD4_PCC3_SLOT                 = 4,
 156         RSVD5_PCC3_SLOT                 = 5,
 157         RSVD6_PCC3_SLOT                 = 6,
 158         RSVD7_PCC3_SLOT                 = 7,
 159         RSVD8_PCC3_SLOT                 = 8,
 160         RSVD9_PCC3_SLOT                 = 9,
 161         RSVD10_PCC3_SLOT                = 10,
 162         RSVD11_PCC3_SLOT                = 11,
 163         RSVD12_PCC3_SLOT                = 12,
 164         RSVD13_PCC3_SLOT                = 13,
 165         RSVD14_PCC3_SLOT                = 14,
 166         RSVD15_PCC3_SLOT                = 15,
 167         ROMCP1_PCC3_SLOT                = 16,
 168         RSVD17_PCC3_SLOT                = 17,
 169         RSVD18_PCC3_SLOT                = 18,
 170         RSVD19_PCC3_SLOT                = 19,
 171         RSVD20_PCC3_SLOT                = 20,
 172         RSVD21_PCC3_SLOT                = 21,
 173         RSVD22_PCC3_SLOT                = 22,
 174         RSVD23_PCC3_SLOT                = 23,
 175         RSVD24_PCC3_SLOT                = 24,
 176         RSVD25_PCC3_SLOT                = 25,
 177         RSVD26_PCC3_SLOT                = 26,
 178         RSVD27_PCC3_SLOT                = 27,
 179         RSVD28_PCC3_SLOT                = 28,
 180         RSVD29_PCC3_SLOT                = 29,
 181         RSVD30_PCC3_SLOT                = 30,
 182         RSVD31_PCC3_SLOT                = 31,
 183
 184         /* Off-Platform (96 entries) */
 185         RSVD32_PCC3_SLOT                = 32,
 186         LPTPM6_PCC3_SLOT                = 33,
 187         LPTPM7_PCC3_SLOT                = 34,
 188         RSVD35_PCC3_SLOT                = 35,
 189         LPI2C6_PCC3_SLOT                = 36,
 190         LPI2C7_PCC3_SLOT                = 37,
 191         LPUART6_PCC3_SLOT               = 38,
 192         LPUART7_PCC3_SLOT               = 39,
 193         VIU0_PCC3_SLOT                  = 40,
 194         DSI0_PCC3_SLOT                  = 41,
 195         LCDIF0_PCC3_SLOT                = 42,
 196         MMDC0_PCC3_SLOT                 = 43,
 197         IOMUXC1_PCC3_SLOT               = 44,
 198         IOMUXC_DDR_PCC3_SLOT            = 45,
 199         PORTC_PCC3_SLOT                 = 46,
 200         PORTD_PCC3_SLOT                 = 47,
 201         PORTE_PCC3_SLOT                 = 48,
 202         PORTF_PCC3_SLOT                 = 49,
 203         RSVD50_PCC3_SLOT                = 50,
 204         PCC3_PCC3_SLOT                  = 51,
 205         RSVD52_PCC3_SLOT                = 52,
 206         WKPU_PCC3_SLOT                  = 53,
 207         RSVD54_PCC3_SLOT                = 54,
 208         RSVD55_PCC3_SLOT                = 55,
 209         RSVD56_PCC3_SLOT                = 56,
 210         RSVD57_PCC3_SLOT                = 57,
 211         RSVD58_PCC3_SLOT                = 58,
 212         RSVD59_PCC3_SLOT                = 59,
 213         RSVD60_PCC3_SLOT                = 60,
 214         RSVD61_PCC3_SLOT                = 61,
 215         RSVD62_PCC3_SLOT                = 62,
 216         RSVD63_PCC3_SLOT                = 63,
 217         RSVD64_PCC3_SLOT                = 64,
 218         RSVD65_PCC3_SLOT                = 65,
 219         RSVD66_PCC3_SLOT                = 66,
 220         RSVD67_PCC3_SLOT                = 67,
 221         RSVD68_PCC3_SLOT                = 68,
 222         RSVD69_PCC3_SLOT                = 69,
 223         RSVD70_PCC3_SLOT                = 70,
 224         RSVD71_PCC3_SLOT                = 71,
 225         RSVD72_PCC3_SLOT                = 72,
 226         RSVD73_PCC3_SLOT                = 73,
 227         RSVD74_PCC3_SLOT                = 74,
 228         RSVD75_PCC3_SLOT                = 75,
 229         RSVD76_PCC3_SLOT                = 76,
 230         RSVD77_PCC3_SLOT                = 77,
 231         RSVD78_PCC3_SLOT                = 78,
 232         RSVD79_PCC3_SLOT                = 79,
 233         RSVD80_PCC3_SLOT                = 80,
 234         GPU3D_PCC3_SLOT                 = 81,
 235         GPU2D_PCC3_SLOT                 = 82,
 236         RSVD83_PCC3_SLOT                = 83,
 237         RSVD84_PCC3_SLOT                = 84,
 238         RSVD85_PCC3_SLOT                = 85,
 239         RSVD86_PCC3_SLOT                = 86,
 240         RSVD87_PCC3_SLOT                = 87,
 241         RSVD88_PCC3_SLOT                = 88,
 242         RSVD89_PCC3_SLOT                = 89,
 243         RSVD90_PCC3_SLOT                = 90,
 244         RSVD91_PCC3_SLOT                = 91,
 245         RSVD92_PCC3_SLOT                = 92,
 246         RSVD93_PCC3_SLOT                = 93,
 247         RSVD94_PCC3_SLOT                = 94,
 248         RSVD95_PCC3_SLOT                = 95,
 249         RSVD96_PCC3_SLOT                = 96,
 250         RSVD97_PCC3_SLOT                = 97,
 251         RSVD98_PCC3_SLOT                = 98,
 252         RSVD99_PCC3_SLOT                = 99,
 253         RSVD100_PCC3_SLOT               = 100,
 254         RSVD101_PCC3_SLOT               = 101,
 255         RSVD102_PCC3_SLOT               = 102,
 256         RSVD103_PCC3_SLOT               = 103,
 257         RSVD104_PCC3_SLOT               = 104,
 258         RSVD105_PCC3_SLOT               = 105,
 259         RSVD106_PCC3_SLOT               = 106,
 260         RSVD107_PCC3_SLOT               = 107,
 261         RSVD108_PCC3_SLOT               = 108,
 262         RSVD109_PCC3_SLOT               = 109,
 263         RSVD110_PCC3_SLOT               = 110,
 264         RSVD111_PCC3_SLOT               = 111,
 265         RSVD112_PCC3_SLOT               = 112,
 266         RSVD113_PCC3_SLOT               = 113,
 267         RSVD114_PCC3_SLOT               = 114,
 268         RSVD115_PCC3_SLOT               = 115,
 269         RSVD116_PCC3_SLOT               = 116,
 270         RSVD117_PCC3_SLOT               = 117,
 271         RSVD118_PCC3_SLOT               = 118,
 272         RSVD119_PCC3_SLOT               = 119,
 273         RSVD120_PCC3_SLOT               = 120,
 274         RSVD121_PCC3_SLOT               = 121,
 275         RSVD122_PCC3_SLOT               = 122,
 276         RSVD123_PCC3_SLOT               = 123,
 277         RSVD124_PCC3_SLOT               = 124,
 278         RSVD125_PCC3_SLOT               = 125,
 279         RSVD126_PCC3_SLOT               = 126,
 280         RSVD127_PCC3_SLOT               = 127,
 281 };
 282
 283
 284 /* PCC registers */
 285 #define PCC_PR_OFFSET   31
 286 #define PCC_PR_MASK             (0x1 << PCC_PR_OFFSET)
 287 #define PCC_CGC_OFFSET  30
 288 #define PCC_CGC_MASK    (0x1 << PCC_CGC_OFFSET)
 289 #define PCC_INUSE_OFFSET        29
 290 #define PCC_INUSE_MASK          (0x1 << PCC_INUSE_OFFSET)
 291 #define PCC_PCS_OFFSET  24
 292 #define PCC_PCS_MASK    (0x7 << PCC_PCS_OFFSET)
 293 #define PCC_FRAC_OFFSET 4
 294 #define PCC_FRAC_MASK   (0x1 << PCC_FRAC_OFFSET)
 295 #define PCC_PCD_OFFSET  0
 296 #define PCC_PCD_MASK    (0xf << PCC_PCD_OFFSET)
 297
 298
 299 enum pcc_clksrc_type {
 300         CLKSRC_PER_PLAT = 0,
 301         CLKSRC_PER_BUS = 1,
 302         CLKSRC_NO_PCS = 2,
 303 };
 304
 305 enum pcc_div_type {
 306         PCC_HAS_DIV,
 307         PCC_NO_DIV,
 308 };
 309
 310 /* All peripheral clocks on A7 PCCs */
 311 enum pcc_clk {
 312         /*PCC2 clocks*/
 313         PER_CLK_DMA1 = 0,
 314         PER_CLK_RGPIO2P1,
 315         PER_CLK_FLEXBUS,
 316         PER_CLK_SEMA42_1,
 317         PER_CLK_DMA_MUX1,
 318         PER_CLK_SNVS,
 319         PER_CLK_CAAM,
 320         PER_CLK_LPTPM4,
 321         PER_CLK_LPTPM5,
 322         PER_CLK_LPIT1,
 323         PER_CLK_LPSPI2,
 324         PER_CLK_LPSPI3,
 325         PER_CLK_LPI2C4,
 326         PER_CLK_LPI2C5,
 327         PER_CLK_LPUART4,
 328         PER_CLK_LPUART5,
 329         PER_CLK_FLEXIO1,
 330         PER_CLK_USB0,
 331         PER_CLK_USB1,
 332         PER_CLK_USB_PHY,
 333         PER_CLK_USB_PL301,
 334         PER_CLK_USDHC0,
 335         PER_CLK_USDHC1,
 336         PER_CLK_WDG1,
 337         PER_CLK_WDG2,
 338
 339         /*PCC3 clocks*/
 340         PER_CLK_LPTPM6,
 341         PER_CLK_LPTPM7,
 342         PER_CLK_LPI2C6,
 343         PER_CLK_LPI2C7,
 344         PER_CLK_LPUART6,
 345         PER_CLK_LPUART7,
 346         PER_CLK_VIU,
 347         PER_CLK_DSI,
 348         PER_CLK_LCDIF,
 349         PER_CLK_MMDC,
 350         PER_CLK_PCTLC,
 351         PER_CLK_PCTLD,
 352         PER_CLK_PCTLE,
 353         PER_CLK_PCTLF,
 354         PER_CLK_GPU3D,
 355         PER_CLK_GPU2D,
 356 };
 357
 358
 359 /* This structure keeps info for each pcc slot */
 360 struct pcc_entry {
 361         u32 pcc_base;
 362         u32 pcc_slot;
 363         enum pcc_clksrc_type clksrc;
 364         enum pcc_div_type div;
 365 };
 366
 367 int pcc_clock_enable(enum pcc_clk clk, bool enable);
 368 int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src);
 369 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);
 370 bool pcc_clock_is_enable(enum pcc_clk clk);
 371 int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src);
 372 u32 pcc_clock_get_rate(enum pcc_clk clk);
 373 #endif