2 * Copyright 2016 Freescale Semiconductors, Inc.
4 * I2CLP driver for i.MX
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __IMX_LPI2C_H__
10 #define __IMX_LPI2C_H__
12 struct imx_lpi2c_bus {
17 struct i2c_pads_info *pads_info;
21 struct imx_lpi2c_reg {
64 typedef enum lpi2c_status {
71 LPI2C_PIN_LOW_TIMEOUT_ERR,
80 /* ----------------------------------------------------------------------------
81 -- LPI2C Register Masks
82 ---------------------------------------------------------------------------- */
85 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
89 /*! @name VERID - Version ID Register */
90 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
91 #define LPI2C_VERID_FEATURE_SHIFT (0U)
92 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
93 #define LPI2C_VERID_MINOR_MASK (0xFF0000U)
94 #define LPI2C_VERID_MINOR_SHIFT (16U)
95 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
96 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
97 #define LPI2C_VERID_MAJOR_SHIFT (24U)
98 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
100 /*! @name PARAM - Parameter Register */
101 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
102 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
103 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
104 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
105 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
106 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
108 /*! @name MCR - Master Control Register */
109 #define LPI2C_MCR_MEN_MASK (0x1U)
110 #define LPI2C_MCR_MEN_SHIFT (0U)
111 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
112 #define LPI2C_MCR_RST_MASK (0x2U)
113 #define LPI2C_MCR_RST_SHIFT (1U)
114 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
115 #define LPI2C_MCR_DOZEN_MASK (0x4U)
116 #define LPI2C_MCR_DOZEN_SHIFT (2U)
117 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
118 #define LPI2C_MCR_DBGEN_MASK (0x8U)
119 #define LPI2C_MCR_DBGEN_SHIFT (3U)
120 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
121 #define LPI2C_MCR_RTF_MASK (0x100U)
122 #define LPI2C_MCR_RTF_SHIFT (8U)
123 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
124 #define LPI2C_MCR_RRF_MASK (0x200U)
125 #define LPI2C_MCR_RRF_SHIFT (9U)
126 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
128 /*! @name MSR - Master Status Register */
129 #define LPI2C_MSR_TDF_MASK (0x1U)
130 #define LPI2C_MSR_TDF_SHIFT (0U)
131 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
132 #define LPI2C_MSR_RDF_MASK (0x2U)
133 #define LPI2C_MSR_RDF_SHIFT (1U)
134 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
135 #define LPI2C_MSR_EPF_MASK (0x100U)
136 #define LPI2C_MSR_EPF_SHIFT (8U)
137 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
138 #define LPI2C_MSR_SDF_MASK (0x200U)
139 #define LPI2C_MSR_SDF_SHIFT (9U)
140 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
141 #define LPI2C_MSR_NDF_MASK (0x400U)
142 #define LPI2C_MSR_NDF_SHIFT (10U)
143 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
144 #define LPI2C_MSR_ALF_MASK (0x800U)
145 #define LPI2C_MSR_ALF_SHIFT (11U)
146 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
147 #define LPI2C_MSR_FEF_MASK (0x1000U)
148 #define LPI2C_MSR_FEF_SHIFT (12U)
149 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
150 #define LPI2C_MSR_PLTF_MASK (0x2000U)
151 #define LPI2C_MSR_PLTF_SHIFT (13U)
152 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
153 #define LPI2C_MSR_DMF_MASK (0x4000U)
154 #define LPI2C_MSR_DMF_SHIFT (14U)
155 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
156 #define LPI2C_MSR_MBF_MASK (0x1000000U)
157 #define LPI2C_MSR_MBF_SHIFT (24U)
158 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
159 #define LPI2C_MSR_BBF_MASK (0x2000000U)
160 #define LPI2C_MSR_BBF_SHIFT (25U)
161 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
163 /*! @name MIER - Master Interrupt Enable Register */
164 #define LPI2C_MIER_TDIE_MASK (0x1U)
165 #define LPI2C_MIER_TDIE_SHIFT (0U)
166 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
167 #define LPI2C_MIER_RDIE_MASK (0x2U)
168 #define LPI2C_MIER_RDIE_SHIFT (1U)
169 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
170 #define LPI2C_MIER_EPIE_MASK (0x100U)
171 #define LPI2C_MIER_EPIE_SHIFT (8U)
172 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
173 #define LPI2C_MIER_SDIE_MASK (0x200U)
174 #define LPI2C_MIER_SDIE_SHIFT (9U)
175 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
176 #define LPI2C_MIER_NDIE_MASK (0x400U)
177 #define LPI2C_MIER_NDIE_SHIFT (10U)
178 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
179 #define LPI2C_MIER_ALIE_MASK (0x800U)
180 #define LPI2C_MIER_ALIE_SHIFT (11U)
181 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
182 #define LPI2C_MIER_FEIE_MASK (0x1000U)
183 #define LPI2C_MIER_FEIE_SHIFT (12U)
184 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
185 #define LPI2C_MIER_PLTIE_MASK (0x2000U)
186 #define LPI2C_MIER_PLTIE_SHIFT (13U)
187 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
188 #define LPI2C_MIER_DMIE_MASK (0x4000U)
189 #define LPI2C_MIER_DMIE_SHIFT (14U)
190 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
192 /*! @name MDER - Master DMA Enable Register */
193 #define LPI2C_MDER_TDDE_MASK (0x1U)
194 #define LPI2C_MDER_TDDE_SHIFT (0U)
195 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
196 #define LPI2C_MDER_RDDE_MASK (0x2U)
197 #define LPI2C_MDER_RDDE_SHIFT (1U)
198 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
200 /*! @name MCFGR0 - Master Configuration Register 0 */
201 #define LPI2C_MCFGR0_HREN_MASK (0x1U)
202 #define LPI2C_MCFGR0_HREN_SHIFT (0U)
203 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
204 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
205 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
206 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
207 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
208 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
209 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
210 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
211 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
212 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
213 #define LPI2C_MCFGR0_RDMO_MASK (0x200U)
214 #define LPI2C_MCFGR0_RDMO_SHIFT (9U)
215 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
217 /*! @name MCFGR1 - Master Configuration Register 1 */
218 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
219 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
220 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
221 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
222 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
223 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
224 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
225 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
226 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
227 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
228 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
229 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
230 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
231 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
232 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
233 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
234 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
235 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
237 /*! @name MCFGR2 - Master Configuration Register 2 */
238 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
239 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
240 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
241 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
242 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
243 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
244 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
245 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
246 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
248 /*! @name MCFGR3 - Master Configuration Register 3 */
249 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
250 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
251 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
253 /*! @name MDMR - Master Data Match Register */
254 #define LPI2C_MDMR_MATCH0_MASK (0xFFU)
255 #define LPI2C_MDMR_MATCH0_SHIFT (0U)
256 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
257 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
258 #define LPI2C_MDMR_MATCH1_SHIFT (16U)
259 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
261 /*! @name MCCR0 - Master Clock Configuration Register 0 */
262 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
263 #define LPI2C_MCCR0_CLKLO_SHIFT (0U)
264 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
265 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
266 #define LPI2C_MCCR0_CLKHI_SHIFT (8U)
267 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
268 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
269 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
270 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
271 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
272 #define LPI2C_MCCR0_DATAVD_SHIFT (24U)
273 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
275 /*! @name MCCR1 - Master Clock Configuration Register 1 */
276 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
277 #define LPI2C_MCCR1_CLKLO_SHIFT (0U)
278 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
279 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
280 #define LPI2C_MCCR1_CLKHI_SHIFT (8U)
281 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
282 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
283 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
284 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
285 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
286 #define LPI2C_MCCR1_DATAVD_SHIFT (24U)
287 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
289 /*! @name MFCR - Master FIFO Control Register */
290 #define LPI2C_MFCR_TXWATER_MASK (0xFFU)
291 #define LPI2C_MFCR_TXWATER_SHIFT (0U)
292 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
293 #define LPI2C_MFCR_RXWATER_MASK (0xFF0000U)
294 #define LPI2C_MFCR_RXWATER_SHIFT (16U)
295 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
297 /*! @name MFSR - Master FIFO Status Register */
298 #define LPI2C_MFSR_TXCOUNT_MASK (0xFFU)
299 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
300 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
301 #define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U)
302 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
303 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
305 /*! @name MTDR - Master Transmit Data Register */
306 #define LPI2C_MTDR_DATA_MASK (0xFFU)
307 #define LPI2C_MTDR_DATA_SHIFT (0U)
308 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
309 #define LPI2C_MTDR_CMD_MASK (0x700U)
310 #define LPI2C_MTDR_CMD_SHIFT (8U)
311 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
313 /*! @name MRDR - Master Receive Data Register */
314 #define LPI2C_MRDR_DATA_MASK (0xFFU)
315 #define LPI2C_MRDR_DATA_SHIFT (0U)
316 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
317 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
318 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
319 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
321 /*! @name SCR - Slave Control Register */
322 #define LPI2C_SCR_SEN_MASK (0x1U)
323 #define LPI2C_SCR_SEN_SHIFT (0U)
324 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
325 #define LPI2C_SCR_RST_MASK (0x2U)
326 #define LPI2C_SCR_RST_SHIFT (1U)
327 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
328 #define LPI2C_SCR_FILTEN_MASK (0x10U)
329 #define LPI2C_SCR_FILTEN_SHIFT (4U)
330 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
331 #define LPI2C_SCR_FILTDZ_MASK (0x20U)
332 #define LPI2C_SCR_FILTDZ_SHIFT (5U)
333 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
334 #define LPI2C_SCR_RTF_MASK (0x100U)
335 #define LPI2C_SCR_RTF_SHIFT (8U)
336 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
337 #define LPI2C_SCR_RRF_MASK (0x200U)
338 #define LPI2C_SCR_RRF_SHIFT (9U)
339 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
341 /*! @name SSR - Slave Status Register */
342 #define LPI2C_SSR_TDF_MASK (0x1U)
343 #define LPI2C_SSR_TDF_SHIFT (0U)
344 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
345 #define LPI2C_SSR_RDF_MASK (0x2U)
346 #define LPI2C_SSR_RDF_SHIFT (1U)
347 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
348 #define LPI2C_SSR_AVF_MASK (0x4U)
349 #define LPI2C_SSR_AVF_SHIFT (2U)
350 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
351 #define LPI2C_SSR_TAF_MASK (0x8U)
352 #define LPI2C_SSR_TAF_SHIFT (3U)
353 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
354 #define LPI2C_SSR_RSF_MASK (0x100U)
355 #define LPI2C_SSR_RSF_SHIFT (8U)
356 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
357 #define LPI2C_SSR_SDF_MASK (0x200U)
358 #define LPI2C_SSR_SDF_SHIFT (9U)
359 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
360 #define LPI2C_SSR_BEF_MASK (0x400U)
361 #define LPI2C_SSR_BEF_SHIFT (10U)
362 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
363 #define LPI2C_SSR_FEF_MASK (0x800U)
364 #define LPI2C_SSR_FEF_SHIFT (11U)
365 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
366 #define LPI2C_SSR_AM0F_MASK (0x1000U)
367 #define LPI2C_SSR_AM0F_SHIFT (12U)
368 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
369 #define LPI2C_SSR_AM1F_MASK (0x2000U)
370 #define LPI2C_SSR_AM1F_SHIFT (13U)
371 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
372 #define LPI2C_SSR_GCF_MASK (0x4000U)
373 #define LPI2C_SSR_GCF_SHIFT (14U)
374 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
375 #define LPI2C_SSR_SARF_MASK (0x8000U)
376 #define LPI2C_SSR_SARF_SHIFT (15U)
377 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
378 #define LPI2C_SSR_SBF_MASK (0x1000000U)
379 #define LPI2C_SSR_SBF_SHIFT (24U)
380 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
381 #define LPI2C_SSR_BBF_MASK (0x2000000U)
382 #define LPI2C_SSR_BBF_SHIFT (25U)
383 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
385 /*! @name SIER - Slave Interrupt Enable Register */
386 #define LPI2C_SIER_TDIE_MASK (0x1U)
387 #define LPI2C_SIER_TDIE_SHIFT (0U)
388 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
389 #define LPI2C_SIER_RDIE_MASK (0x2U)
390 #define LPI2C_SIER_RDIE_SHIFT (1U)
391 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
392 #define LPI2C_SIER_AVIE_MASK (0x4U)
393 #define LPI2C_SIER_AVIE_SHIFT (2U)
394 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
395 #define LPI2C_SIER_TAIE_MASK (0x8U)
396 #define LPI2C_SIER_TAIE_SHIFT (3U)
397 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
398 #define LPI2C_SIER_RSIE_MASK (0x100U)
399 #define LPI2C_SIER_RSIE_SHIFT (8U)
400 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
401 #define LPI2C_SIER_SDIE_MASK (0x200U)
402 #define LPI2C_SIER_SDIE_SHIFT (9U)
403 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
404 #define LPI2C_SIER_BEIE_MASK (0x400U)
405 #define LPI2C_SIER_BEIE_SHIFT (10U)
406 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
407 #define LPI2C_SIER_FEIE_MASK (0x800U)
408 #define LPI2C_SIER_FEIE_SHIFT (11U)
409 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
410 #define LPI2C_SIER_AM0IE_MASK (0x1000U)
411 #define LPI2C_SIER_AM0IE_SHIFT (12U)
412 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
413 #define LPI2C_SIER_AM1F_MASK (0x2000U)
414 #define LPI2C_SIER_AM1F_SHIFT (13U)
415 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
416 #define LPI2C_SIER_GCIE_MASK (0x4000U)
417 #define LPI2C_SIER_GCIE_SHIFT (14U)
418 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
419 #define LPI2C_SIER_SARIE_MASK (0x8000U)
420 #define LPI2C_SIER_SARIE_SHIFT (15U)
421 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
423 /*! @name SDER - Slave DMA Enable Register */
424 #define LPI2C_SDER_TDDE_MASK (0x1U)
425 #define LPI2C_SDER_TDDE_SHIFT (0U)
426 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
427 #define LPI2C_SDER_RDDE_MASK (0x2U)
428 #define LPI2C_SDER_RDDE_SHIFT (1U)
429 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
430 #define LPI2C_SDER_AVDE_MASK (0x4U)
431 #define LPI2C_SDER_AVDE_SHIFT (2U)
432 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
434 /*! @name SCFGR1 - Slave Configuration Register 1 */
435 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
436 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
437 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
438 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
439 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
440 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
441 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
442 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
443 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
444 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
445 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
446 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
447 #define LPI2C_SCFGR1_GCEN_MASK (0x100U)
448 #define LPI2C_SCFGR1_GCEN_SHIFT (8U)
449 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
450 #define LPI2C_SCFGR1_SAEN_MASK (0x200U)
451 #define LPI2C_SCFGR1_SAEN_SHIFT (9U)
452 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
453 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
454 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
455 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
456 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
457 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
458 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
459 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
460 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
461 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
462 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
463 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
464 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
465 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
466 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
467 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
469 /*! @name SCFGR2 - Slave Configuration Register 2 */
470 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
471 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
472 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
473 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
474 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
475 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
476 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
477 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
478 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
479 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
480 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
481 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
483 /*! @name SAMR - Slave Address Match Register */
484 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
485 #define LPI2C_SAMR_ADDR0_SHIFT (1U)
486 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
487 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
488 #define LPI2C_SAMR_ADDR1_SHIFT (17U)
489 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
491 /*! @name SASR - Slave Address Status Register */
492 #define LPI2C_SASR_RADDR_MASK (0x7FFU)
493 #define LPI2C_SASR_RADDR_SHIFT (0U)
494 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
495 #define LPI2C_SASR_ANV_MASK (0x4000U)
496 #define LPI2C_SASR_ANV_SHIFT (14U)
497 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
499 /*! @name STAR - Slave Transmit ACK Register */
500 #define LPI2C_STAR_TXNACK_MASK (0x1U)
501 #define LPI2C_STAR_TXNACK_SHIFT (0U)
502 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
504 /*! @name STDR - Slave Transmit Data Register */
505 #define LPI2C_STDR_DATA_MASK (0xFFU)
506 #define LPI2C_STDR_DATA_SHIFT (0U)
507 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
509 /*! @name SRDR - Slave Receive Data Register */
510 #define LPI2C_SRDR_DATA_MASK (0xFFU)
511 #define LPI2C_SRDR_DATA_SHIFT (0U)
512 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
513 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
514 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
515 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
516 #define LPI2C_SRDR_SOF_MASK (0x8000U)
517 #define LPI2C_SRDR_SOF_SHIFT (15U)
518 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
520 #endif /* __ASM_ARCH_IMX_I2C_H__ */