1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
8 #ifdef CONFIG_ROM_UNIFIED_SECTIONS
9 #define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
10 #define ROM_VERSION_OFFSET 0x80
12 #define ROM_API_TABLE_BASE_ADDR_LEGACY 0xC0
13 #define ROM_VERSION_OFFSET 0x48
15 #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 0xC4
16 #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 0xC4
17 #define ROM_API_HWCNFG_SETUP_OFFSET 0x08
18 #define ROM_VERSION_TO10 0x10
19 #define ROM_VERSION_TO12 0x12
20 #define ROM_VERSION_TO15 0x15
31 * The following is to fill in those arguments for this ROM function
32 * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
33 * This function is used to copy data from the storage media into DDR.
34 * start - Initial (possibly partial) image load address on entry.
35 * Final image load address on exit.
36 * bytes - Initial (possibly partial) image size on entry.
37 * Final image size on exit.
38 * boot_data - Initial @ref ivt Boot Data load address.
44 #ifdef CONFIG_NOR_BOOT
46 ldr r3, =ROM_VERSION_OFFSET
48 cmp r4, #ROM_VERSION_TO10
49 bgt before_calling_rom___pu_irom_hwcnfg_setup
61 * check the _pu_irom_api_table for the address
63 before_calling_rom___pu_irom_hwcnfg_setup:
64 ldr r3, =ROM_VERSION_OFFSET
66 #if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
67 ldr r3, =ROM_VERSION_TO12
69 ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
70 ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
71 #elif defined(CONFIG_MX6Q)
72 ldr r3, =ROM_VERSION_TO15
74 ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
75 ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
77 ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
79 ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
81 after_calling_rom___pu_irom_hwcnfg_setup:
84 * ROM_API_HWCNFG_SETUP function enables MMU & Caches.
85 * Thus disable MMU & Caches.
88 mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0*/
89 ands r0, r0, #0x1 /* check if MMU is enabled */
90 beq mmu_disable_notreq /* exit if MMU is already disabled */
92 /* Disable caches, MMU */
93 mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 into r0 */
94 bic r0, r0, #(1 << 2) /* disable D Cache */
95 bic r0, r0, #0x1 /* clear bit 0 ; MMU off */
97 bic r0, r0, #(0x1 << 11) /* disable Z, branch prediction */
98 bic r0, r0, #(0x1 << 1) /* disable A, Strict alignment */
100 mcr p15, 0, r0, c1, c0, 0 /* write CP15 register 1 */
109 /* To return to ROM from plugin, we need to fill in these argument.
110 * Here is what need to do:
111 * Need to construct the paramters for this function before return to ROM:
112 * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
120 ldr r5, second_ivt_offset
125 /* return back to ROM code */
128 /* make the following data right in the end of the output*/
131 #if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT))
132 #define FLASH_OFFSET 0x1000
134 #define FLASH_OFFSET 0x400
138 * second_ivt_offset is the offset from the "second_ivt_header" to
139 * "image_copy_start", which involves FLASH_OFFSET, plus the first
140 * ivt_header, the plugin code size itself recorded by "ivt2_header"
143 second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET)
146 * The following is the second IVT header plus the second boot data
148 ivt2_header: .long 0x0
149 app2_code_jump_v: .long 0x0
152 boot_data2_ptr: .long 0x0
154 app_code_csf2: .long 0x0
156 boot_data2: .long 0x0
157 image_len2: .long 0x0