2 * Copyright (C) 2013 Boundary Devices Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __ASM_ARCH_MX6_DDR_H__
7 #define __ASM_ARCH_MX6_DDR_H__
9 #ifndef CONFIG_SPL_BUILD
13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 #include "mx6dl-ddr.h"
17 #include "mx6sx-ddr.h"
20 #include "mx6ul-ddr.h"
23 #include "mx6sl-ddr.h"
25 #error "Please select cpu"
26 #endif /* CONFIG_MX6SL */
27 #endif /* CONFIG_MX6UL */
28 #endif /* CONFIG_MX6SX */
29 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
30 #endif /* CONFIG_MX6Q */
33 /* MMDC P0/P1 Registers */
120 #define MX6SL_IOM_DDR_BASE 0x020e0300
121 struct mx6sl_iomux_ddr_regs {
146 #define MX6SL_IOM_GRP_BASE 0x020e0500
147 struct mx6sl_iomux_grp_regs {
163 #define MX6UL_IOM_DDR_BASE 0x020e0200
164 struct mx6ul_iomux_ddr_regs {
186 #define MX6UL_IOM_GRP_BASE 0x020e0400
187 struct mx6ul_iomux_grp_regs {
201 #define MX6SX_IOM_DDR_BASE 0x020e0200
202 struct mx6sx_iomux_ddr_regs {
227 #define MX6SX_IOM_GRP_BASE 0x020e0500
228 struct mx6sx_iomux_grp_regs {
245 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
247 #define MX6DQ_IOM_DDR_BASE 0x020e0500
248 struct mx6dq_iomux_ddr_regs {
282 #define MX6DQ_IOM_GRP_BASE 0x020e0700
283 struct mx6dq_iomux_grp_regs {
305 #define MX6SDL_IOM_DDR_BASE 0x020e0400
306 struct mx6sdl_iomux_ddr_regs {
338 #define MX6SDL_IOM_GRP_BASE 0x020e0700
339 struct mx6sdl_iomux_grp_regs {
360 /* Device Information: Varies per DDR3 part number and speed grade */
361 struct mx6_ddr3_cfg {
362 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
363 u8 density; /* chip density (Gb) (1,2,4,8) */
364 u8 width; /* bus width (bits) (4,8,16) */
365 u8 banks; /* number of banks */
366 u8 rowaddr; /* row address bits (11-16)*/
367 u8 coladdr; /* col address bits (9-12) */
368 u8 pagesz; /* page size (K) (1-2) */
369 u16 trcd; /* tRCD=tRP=CL (ns*100) */
370 u16 trcmin; /* tRC min (ns*100) */
371 u16 trasmin; /* tRAS min (ns*100) */
372 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
375 /* System Information: Varies per board design, layout, and term choices */
376 struct mx6_ddr_sysinfo {
377 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
378 u8 cs_density; /* density per chip select (Gb) */
379 u8 ncs; /* number chip selects used (1|2) */
380 char cs1_mirror;/* enable address mirror (0|1) */
381 char bi_on; /* Bank interleaving enable */
382 u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
383 u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
384 u8 ralat; /* Read Additional Latency (0-7) */
385 u8 walat; /* Write Additional Latency (0-3) */
386 u8 mif3_mode; /* Command prediction working mode */
387 u8 rst_to_cke; /* Time from SDE enable to CKE rise */
388 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
389 u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
393 * Board specific calibration:
394 * This includes write leveling calibration values as well as DQS gating
395 * and read/write delays. These values are board/layout/device specific.
396 * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
397 * (DOC-96412) to determine these values over a range of boards and
400 struct mx6_mmdc_calibration {
401 /* write leveling calibration */
406 /* read DQS gating */
417 /* lpddr2 zq hw calibration */
421 /* configure iomux (pinctl/padctl) */
422 void mx6dq_dram_iocfg(unsigned width,
423 const struct mx6dq_iomux_ddr_regs *,
424 const struct mx6dq_iomux_grp_regs *);
425 void mx6sdl_dram_iocfg(unsigned width,
426 const struct mx6sdl_iomux_ddr_regs *,
427 const struct mx6sdl_iomux_grp_regs *);
428 void mx6sx_dram_iocfg(unsigned width,
429 const struct mx6sx_iomux_ddr_regs *,
430 const struct mx6sx_iomux_grp_regs *);
431 void mx6ul_dram_iocfg(unsigned width,
432 const struct mx6ul_iomux_ddr_regs *,
433 const struct mx6ul_iomux_grp_regs *);
434 void mx6sl_dram_iocfg(unsigned width,
435 const struct mx6sl_iomux_ddr_regs *,
436 const struct mx6sl_iomux_grp_regs *);
438 /* configure mx6 mmdc registers */
439 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
440 const struct mx6_mmdc_calibration *,
441 const struct mx6_ddr3_cfg *);
443 #endif /* CONFIG_SPL_BUILD */
445 #define MX6_MMDC_P0_MDCTL 0x021b0000
446 #define MX6_MMDC_P0_MDPDC 0x021b0004
447 #define MX6_MMDC_P0_MDOTC 0x021b0008
448 #define MX6_MMDC_P0_MDCFG0 0x021b000c
449 #define MX6_MMDC_P0_MDCFG1 0x021b0010
450 #define MX6_MMDC_P0_MDCFG2 0x021b0014
451 #define MX6_MMDC_P0_MDMISC 0x021b0018
452 #define MX6_MMDC_P0_MDSCR 0x021b001c
453 #define MX6_MMDC_P0_MDREF 0x021b0020
454 #define MX6_MMDC_P0_MDRWD 0x021b002c
455 #define MX6_MMDC_P0_MDOR 0x021b0030
456 #define MX6_MMDC_P0_MDASP 0x021b0040
457 #define MX6_MMDC_P0_MAPSR 0x021b0404
458 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
459 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
460 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
461 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
462 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
463 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
464 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
465 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
466 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
467 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
468 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
469 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
470 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
472 #define MX6_MMDC_P1_MDCTL 0x021b4000
473 #define MX6_MMDC_P1_MDPDC 0x021b4004
474 #define MX6_MMDC_P1_MDOTC 0x021b4008
475 #define MX6_MMDC_P1_MDCFG0 0x021b400c
476 #define MX6_MMDC_P1_MDCFG1 0x021b4010
477 #define MX6_MMDC_P1_MDCFG2 0x021b4014
478 #define MX6_MMDC_P1_MDMISC 0x021b4018
479 #define MX6_MMDC_P1_MDSCR 0x021b401c
480 #define MX6_MMDC_P1_MDREF 0x021b4020
481 #define MX6_MMDC_P1_MDRWD 0x021b402c
482 #define MX6_MMDC_P1_MDOR 0x021b4030
483 #define MX6_MMDC_P1_MDASP 0x021b4040
484 #define MX6_MMDC_P1_MAPSR 0x021b4404
485 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
486 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
487 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
488 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
489 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
490 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
491 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
492 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
493 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
494 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
495 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
496 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
497 #define MX6_MMDC_P1_MPMUR0 0x021b48b8
499 #endif /*__ASM_ARCH_MX6_DDR_H__ */