2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
59 u32 analog_pll_sys; /* 0x4000 */
60 u32 analog_pll_sys_set;
61 u32 analog_pll_sys_clr;
62 u32 analog_pll_sys_tog;
63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
64 u32 analog_usb1_pll_480_ctrl_set;
65 u32 analog_usb1_pll_480_ctrl_clr;
66 u32 analog_usb1_pll_480_ctrl_tog;
67 u32 analog_reserved0[4];
68 u32 analog_pll_528; /* 0x4030 */
69 u32 analog_pll_528_set;
70 u32 analog_pll_528_clr;
71 u32 analog_pll_528_tog;
72 u32 analog_pll_528_ss; /* 0x4040 */
73 u32 analog_reserved1[3];
74 u32 analog_pll_528_num; /* 0x4050 */
75 u32 analog_reserved2[3];
76 u32 analog_pll_528_denom; /* 0x4060 */
77 u32 analog_reserved3[3];
78 u32 analog_pll_audio; /* 0x4070 */
79 u32 analog_pll_audio_set;
80 u32 analog_pll_audio_clr;
81 u32 analog_pll_audio_tog;
82 u32 analog_pll_audio_num; /* 0x4080*/
83 u32 analog_reserved4[3];
84 u32 analog_pll_audio_denom; /* 0x4090 */
85 u32 analog_reserved5[3];
86 u32 analog_pll_video; /* 0x40a0 */
87 u32 analog_pll_video_set;
88 u32 analog_pll_video_clr;
89 u32 analog_pll_video_tog;
90 u32 analog_pll_video_num; /* 0x40b0 */
91 u32 analog_reserved6[3];
92 u32 analog_pll_video_denom; /* 0x40c0 */
93 u32 analog_reserved7[7];
94 u32 analog_pll_enet; /* 0x40e0 */
95 u32 analog_pll_enet_set;
96 u32 analog_pll_enet_clr;
97 u32 analog_pll_enet_tog;
98 u32 analog_pfd_480; /* 0x40f0 */
99 u32 analog_pfd_480_set;
100 u32 analog_pfd_480_clr;
101 u32 analog_pfd_480_tog;
102 u32 analog_pfd_528; /* 0x4100 */
103 u32 analog_pfd_528_set;
104 u32 analog_pfd_528_clr;
105 u32 analog_pfd_528_tog;
109 /* Define the bits in register CCR */
110 #define MXC_CCM_CCR_RBC_EN (1 << 27)
111 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
112 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
113 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
114 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
115 #define MXC_CCM_CCR_COSC_EN (1 << 12)
117 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
119 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
121 #define MXC_CCM_CCR_OSCNT_OFFSET 0
123 /* Define the bits in register CCDR */
124 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
125 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
126 /* Exists on i.MX6QP */
127 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
129 /* Define the bits in register CSR */
130 #define MXC_CCM_CSR_COSC_READY (1 << 5)
131 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
133 /* Define the bits in register CCSR */
134 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
135 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
136 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
137 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
138 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
139 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
140 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
141 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
142 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
143 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
144 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
146 /* Define the bits in register CACRR */
147 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
148 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
150 /* Define the bits in register CBCDR */
151 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
152 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
153 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
154 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
156 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
157 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
159 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
160 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
161 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
162 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
163 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
164 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
165 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
166 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
167 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
168 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
169 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
170 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
172 /* Define the bits in register CBCMR */
173 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
174 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
175 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
176 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
177 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
178 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
179 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
180 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
181 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
182 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
183 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
185 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
186 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
187 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
188 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
190 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
191 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
193 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
195 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
196 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
197 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
198 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
199 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
200 /* Exists on i.MX6QP */
201 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
203 /* Define the bits in register CSCMR1 */
204 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
205 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
207 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
208 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
210 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
211 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
213 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
214 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
215 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
216 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
217 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
218 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
219 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
220 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
221 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
222 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
223 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
224 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
225 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
226 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
227 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
229 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
230 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
232 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
233 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
234 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
236 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
238 /* Define the bits in register CSCMR2 */
240 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
241 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
243 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
244 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
245 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
246 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
247 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
248 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
249 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
251 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
252 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
254 /* Define the bits in register CSCDR1 */
256 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
257 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
259 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
260 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
261 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
262 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
263 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
264 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
265 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
266 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
268 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
269 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
270 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
271 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
273 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
274 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
275 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
276 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
278 /* Define the bits in register CS1CDR */
279 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
280 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
281 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
282 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
283 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
284 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
285 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
286 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
287 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
288 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
289 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
290 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
292 /* Define the bits in register CS2CDR */
294 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
295 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
296 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
297 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
298 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
299 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
300 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
301 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
302 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
304 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
305 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
306 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
307 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
308 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
309 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
311 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
312 (is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
313 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
314 (is_mx6dqp() ? 15 : 16)
315 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
316 (is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
319 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
320 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
321 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
322 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
323 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
324 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
325 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
326 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
328 /* Define the bits in register CDCDR */
330 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
331 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
332 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
334 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
335 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
336 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
337 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
338 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
339 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
340 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
341 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
342 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
343 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
344 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
345 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
347 /* Define the bits in register CHSCCDR */
349 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
350 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
351 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
352 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
353 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
354 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
355 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
356 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
357 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
358 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
359 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
360 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
362 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
363 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
364 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
365 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
366 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
367 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
368 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
369 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
370 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
371 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
372 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
373 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
376 #define CHSCCDR_CLK_SEL_LDB_DI0 3
377 #define CHSCCDR_PODF_DIVIDE_BY_3 2
378 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
380 /* Define the bits in register CSCDR2 */
381 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
382 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
383 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
384 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
386 /* All IPU2_DI1 are LCDIF1 on MX6SX */
387 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
388 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
389 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
390 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
391 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
392 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
393 /* All IPU2_DI0 are LCDIF2 on MX6SX */
394 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
395 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
396 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
397 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
398 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
399 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
401 /* Define the bits in register CSCDR3 */
402 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
403 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
404 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
405 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
406 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
407 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
408 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
409 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
411 /* Define the bits in register CDHIPR */
412 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
413 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
415 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
417 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
418 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
419 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
420 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
422 /* Define the bits in register CLPCR */
423 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
424 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
426 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
427 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
428 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
430 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
431 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
433 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
434 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
436 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
437 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
438 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
439 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
440 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
441 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
442 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
443 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
445 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
446 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
447 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
449 #define MXC_CCM_CLPCR_LPM_MASK 0x3
450 #define MXC_CCM_CLPCR_LPM_OFFSET 0
452 /* Define the bits in register CISR */
453 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
455 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
457 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
458 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
459 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
460 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
461 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
462 #define MXC_CCM_CISR_COSC_READY (1 << 6)
463 #define MXC_CCM_CISR_LRF_PLL 1
465 /* Define the bits in register CIMR */
466 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
468 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
470 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
471 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
472 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
473 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
474 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
475 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
476 #define MXC_CCM_CIMR_MASK_LRF_PLL 1
478 /* Define the bits in register CCOSR */
479 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
480 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
481 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
482 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
483 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
484 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
485 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
486 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
487 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
488 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
489 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
491 /* Define the bits in registers CGPR */
492 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
493 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
494 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
495 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
497 /* Define the bits in registers CCGRx */
498 #define MXC_CCM_CCGR_CG_MASK 3
500 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
501 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
502 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
503 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
504 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
505 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
506 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
507 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
508 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
509 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
510 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
511 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
512 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
513 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
514 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
515 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
516 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
517 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
518 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
519 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
520 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
521 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
522 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
523 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
524 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
525 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
526 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
527 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
529 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
530 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
532 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
533 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
536 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
537 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
538 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
539 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
540 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
541 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
542 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
543 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
544 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
545 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
547 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
548 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
550 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
551 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
552 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
553 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
554 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
555 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
557 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
558 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
560 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
561 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
562 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
563 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
565 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
566 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
568 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
569 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
571 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
572 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
573 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
574 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
578 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
579 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
581 #define MXC_CCM_CCGR2_CSI_OFFSET 2
582 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
585 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
586 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
588 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
589 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
590 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
591 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
592 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
593 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
594 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
595 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
596 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
597 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
598 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
599 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
600 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
601 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
602 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
603 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
604 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
605 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
606 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
607 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
609 #define MXC_CCM_CCGR2_LCD_OFFSET 28
610 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
611 #define MXC_CCM_CCGR2_PXP_OFFSET 30
612 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
614 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
615 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
616 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
617 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
621 #define MXC_CCM_CCGR3_M4_OFFSET 2
622 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
623 #define MXC_CCM_CCGR3_ENET_OFFSET 4
624 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
625 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
626 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
628 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
629 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
630 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
631 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
632 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
633 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
635 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
636 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
637 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
638 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
639 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
640 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
641 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
642 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
644 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
645 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
647 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
648 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
649 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
650 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
652 #define MXC_CCM_CCGR3_MLB_OFFSET 18
653 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
654 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
655 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
657 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
658 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
660 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
661 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
662 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
663 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
664 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
665 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
667 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
668 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
671 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
672 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
674 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
675 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
677 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
678 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
680 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
681 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
682 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
683 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
684 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
685 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
686 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
687 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
688 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
689 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
690 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
691 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
692 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
693 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
694 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
695 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
696 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
697 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
698 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
699 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
701 #define MXC_CCM_CCGR5_ROM_OFFSET 0
702 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
704 #define MXC_CCM_CCGR5_SATA_OFFSET 4
705 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
707 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
708 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
709 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
710 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
711 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
712 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
713 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
714 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
715 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
716 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
717 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
718 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
719 #define MXC_CCM_CCGR5_UART_OFFSET 24
720 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
721 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
722 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
724 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
725 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
726 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
727 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
730 /* PRG_CLK0 exists on i.MX6QP */
731 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24)
733 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
734 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
735 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
736 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
737 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
738 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
739 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
740 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
741 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
742 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
743 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
744 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
745 /* The following *CCGR6* exist only i.MX6SX */
746 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
747 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
748 #define MXC_CCM_CCGR6_VADC_OFFSET 20
749 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
750 #define MXC_CCM_CCGR6_GIS_OFFSET 22
751 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
752 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
753 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
754 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
755 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
756 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
757 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
758 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
759 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
760 /* The two does not exist on i.MX6SX */
761 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
762 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
764 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
765 #define BP_ANADIG_PLL_SYS_RSVD0 20
766 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
767 #define BF_ANADIG_PLL_SYS_RSVD0(v) \
768 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
769 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
770 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
771 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
772 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
773 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
774 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
775 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
776 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
777 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
778 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
779 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
780 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
781 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
782 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
783 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
784 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
785 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
786 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
787 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
788 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
789 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
790 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
791 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
793 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
794 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
795 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
796 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
797 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
798 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
799 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
800 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
801 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
802 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
803 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
804 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
805 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
806 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
807 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
808 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
809 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
810 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
811 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
812 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
813 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
814 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
815 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
816 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
817 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
818 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
819 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
820 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
821 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
822 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
823 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
825 #define BM_ANADIG_PLL_528_LOCK 0x80000000
826 #define BP_ANADIG_PLL_528_RSVD1 19
827 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
828 #define BF_ANADIG_PLL_528_RSVD1(v) \
829 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
830 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
831 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
832 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
833 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
834 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
835 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
836 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
837 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
838 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
839 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
840 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
841 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
842 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
843 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
844 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
845 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
846 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
847 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
848 #define BP_ANADIG_PLL_528_RSVD0 1
849 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
850 #define BF_ANADIG_PLL_528_RSVD0(v) \
851 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
852 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
854 #define BP_ANADIG_PLL_528_SS_STOP 16
855 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
856 #define BF_ANADIG_PLL_528_SS_STOP(v) \
857 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
858 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
859 #define BP_ANADIG_PLL_528_SS_STEP 0
860 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
861 #define BF_ANADIG_PLL_528_SS_STEP(v) \
862 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
864 #define BP_ANADIG_PLL_528_NUM_RSVD0 30
865 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
866 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
867 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
868 #define BP_ANADIG_PLL_528_NUM_A 0
869 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
870 #define BF_ANADIG_PLL_528_NUM_A(v) \
871 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
873 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
874 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
875 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
876 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
877 #define BP_ANADIG_PLL_528_DENOM_B 0
878 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
879 #define BF_ANADIG_PLL_528_DENOM_B(v) \
880 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
882 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
883 #define BP_ANADIG_PLL_AUDIO_RSVD0 22
884 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
885 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
886 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
887 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
888 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
889 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
890 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
891 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
892 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
893 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
894 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
895 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
896 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
897 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
898 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
899 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
900 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
901 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
902 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
903 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
904 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
905 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
906 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
907 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
908 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
909 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
910 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
911 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
912 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
913 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
915 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
916 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
917 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
918 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
919 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
920 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
921 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
922 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
924 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
925 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
926 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
927 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
928 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
929 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
930 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
931 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
933 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
934 #define BP_ANADIG_PLL_VIDEO_RSVD0 22
935 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
936 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
937 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
938 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
939 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
940 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
941 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
942 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
943 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
944 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
945 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
946 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
947 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
948 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
949 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
950 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
951 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
952 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
953 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
954 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
955 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
956 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
957 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
958 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
959 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
960 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
961 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
962 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
963 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
964 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
966 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
967 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
968 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
969 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
970 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
971 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
972 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
973 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
975 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
976 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
977 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
978 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
979 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
980 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
981 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
982 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
984 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
985 #define BP_ANADIG_PLL_ENET_RSVD1 21
986 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
987 #define BF_ANADIG_PLL_ENET_RSVD1(v) \
988 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
989 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
990 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
991 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
992 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
993 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
994 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
995 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
996 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
997 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
998 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
999 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1000 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1001 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1002 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1003 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
1004 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
1005 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1006 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1007 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1008 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1009 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1010 #define BP_ANADIG_PLL_ENET_RSVD0 2
1011 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1012 #define BF_ANADIG_PLL_ENET_RSVD0(v) \
1013 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1014 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1015 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1016 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1017 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1019 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1020 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1021 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1022 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1023 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1024 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1025 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1026 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1027 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1028 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1029 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1030 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1031 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1032 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1033 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1034 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1035 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1036 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1037 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1038 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1039 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1040 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1041 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1042 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1044 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1045 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1046 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1047 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1048 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1049 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1050 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1051 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1052 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1053 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1054 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1055 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1056 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1057 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1058 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1059 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1060 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1061 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1062 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1063 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1064 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1065 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1066 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1067 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1069 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
1071 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
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