1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
7 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
9 #define CCM_CCOSR 0x020c4060
10 #define CCM_CCGR0 0x020C4068
11 #define CCM_CCGR1 0x020C406c
12 #define CCM_CCGR2 0x020C4070
13 #define CCM_CCGR3 0x020C4074
14 #define CCM_CCGR4 0x020C4078
15 #define CCM_CCGR5 0x020C407c
16 #define CCM_CCGR6 0x020C4080
18 #define PMU_MISC2 0x020C8170
26 u32 cacrr; /* 0x0010*/
30 u32 cscmr2; /* 0x0020 */
34 u32 cdcdr; /* 0x0030 */
38 u32 cscdr4; /* 0x0040 */
42 u32 ctor; /* 0x0050 */
46 u32 ccosr; /* 0x0060 */
50 u32 CCGR2; /* 0x0070 */
54 u32 CCGR6; /* 0x0080 */
58 u32 analog_pll_sys; /* 0x4000 */
59 u32 analog_pll_sys_set;
60 u32 analog_pll_sys_clr;
61 u32 analog_pll_sys_tog;
62 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
63 u32 analog_usb1_pll_480_ctrl_set;
64 u32 analog_usb1_pll_480_ctrl_clr;
65 u32 analog_usb1_pll_480_ctrl_tog;
66 u32 analog_reserved0[4];
67 u32 analog_pll_528; /* 0x4030 */
68 u32 analog_pll_528_set;
69 u32 analog_pll_528_clr;
70 u32 analog_pll_528_tog;
71 u32 analog_pll_528_ss; /* 0x4040 */
72 u32 analog_reserved1[3];
73 u32 analog_pll_528_num; /* 0x4050 */
74 u32 analog_reserved2[3];
75 u32 analog_pll_528_denom; /* 0x4060 */
76 u32 analog_reserved3[3];
77 u32 analog_pll_audio; /* 0x4070 */
78 u32 analog_pll_audio_set;
79 u32 analog_pll_audio_clr;
80 u32 analog_pll_audio_tog;
81 u32 analog_pll_audio_num; /* 0x4080*/
82 u32 analog_reserved4[3];
83 u32 analog_pll_audio_denom; /* 0x4090 */
84 u32 analog_reserved5[3];
85 u32 analog_pll_video; /* 0x40a0 */
86 u32 analog_pll_video_set;
87 u32 analog_pll_video_clr;
88 u32 analog_pll_video_tog;
89 u32 analog_pll_video_num; /* 0x40b0 */
90 u32 analog_reserved6[3];
91 u32 analog_pll_video_denom; /* 0x40c0 */
92 u32 analog_reserved7[7];
93 u32 analog_pll_enet; /* 0x40e0 */
94 u32 analog_pll_enet_set;
95 u32 analog_pll_enet_clr;
96 u32 analog_pll_enet_tog;
97 u32 analog_pfd_480; /* 0x40f0 */
98 u32 analog_pfd_480_set;
99 u32 analog_pfd_480_clr;
100 u32 analog_pfd_480_tog;
101 u32 analog_pfd_528; /* 0x4100 */
102 u32 analog_pfd_528_set;
103 u32 analog_pfd_528_clr;
104 u32 analog_pfd_528_tog;
105 /* PMU Memory Map/Register Definition */
119 u32 pmu_reg_core_set;
120 u32 pmu_reg_core_clr;
121 u32 pmu_reg_core_tog;
134 /* TEMPMON Memory Map/Register Definition */
143 /* USB Analog Memory Map/Register Definition */
144 u32 usb1_vbus_detect;
145 u32 usb1_vbus_detect_set;
146 u32 usb1_vbus_detect_clr;
147 u32 usb1_vbus_detect_tog;
148 u32 usb1_chrg_detect;
149 u32 usb1_chrg_detect_set;
150 u32 usb1_chrg_detect_clr;
151 u32 usb1_chrg_detect_tog;
152 u32 usb1_vbus_det_stat;
153 u32 usb1_vbus_det_stat_set;
154 u32 usb1_vbus_det_stat_clr;
155 u32 usb1_vbus_det_stat_tog;
156 u32 usb1_chrg_det_stat;
157 u32 usb1_chrg_det_stat_set;
158 u32 usb1_chrg_det_stat_clr;
159 u32 usb1_chrg_det_stat_tog;
161 u32 usb1_loopback_set;
162 u32 usb1_loopback_clr;
163 u32 usb1_loopback_tog;
168 u32 usb2_vbus_detect;
169 u32 usb2_vbus_detect_set;
170 u32 usb2_vbus_detect_clr;
171 u32 usb2_vbus_detect_tog;
172 u32 usb2_chrg_detect;
173 u32 usb2_chrg_detect_set;
174 u32 usb2_chrg_detect_clr;
175 u32 usb2_chrg_detect_tog;
176 u32 usb2_vbus_det_stat;
177 u32 usb2_vbus_det_stat_set;
178 u32 usb2_vbus_det_stat_clr;
179 u32 usb2_vbus_det_stat_tog;
180 u32 usb2_chrg_det_stat;
181 u32 usb2_chrg_det_stat_set;
182 u32 usb2_chrg_det_stat_clr;
183 u32 usb2_chrg_det_stat_tog;
185 u32 usb2_loopback_set;
186 u32 usb2_loopback_clr;
187 u32 usb2_loopback_tog;
194 /* For i.MX 6SoloLite */
195 u32 digprog_sololite;
199 /* Define the bits in register CCR */
200 #define MXC_CCM_CCR_RBC_EN (1 << 27)
201 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
202 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
203 /* CCR_WB does not exist on i.MX6SX/UL */
204 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
205 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
206 #define MXC_CCM_CCR_COSC_EN (1 << 12)
208 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
210 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
212 #define MXC_CCM_CCR_OSCNT_OFFSET 0
214 /* Define the bits in register CCDR */
215 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
216 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
217 /* Exists on i.MX6QP */
218 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
220 /* Define the bits in register CSR */
221 #define MXC_CCM_CSR_COSC_READY (1 << 5)
222 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
224 /* Define the bits in register CCSR */
225 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
226 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
227 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
228 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
229 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
230 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
231 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
232 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
233 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
234 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
235 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
237 /* Define the bits in register CACRR */
238 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
239 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
241 /* Define the bits in register CBCDR */
242 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
243 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
244 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
245 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
246 /* MMDC_CH0 not exists on i.MX6SX */
247 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
248 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
249 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
250 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
251 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
252 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
253 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
254 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
255 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
256 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
257 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
258 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
259 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
260 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
262 /* Define the bits in register CBCMR */
263 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
264 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
265 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
266 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
267 /* LCDIF on i.MX6SX/UL */
268 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23)
269 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23
270 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
271 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
272 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
273 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
274 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
275 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
276 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
278 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
279 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
280 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
281 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
283 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
284 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
286 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
288 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
289 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
290 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
291 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
292 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
293 /* Exists on i.MX6QP */
294 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
296 /* Define the bits in register CSCMR1 */
297 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
298 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
299 /* QSPI1 exist on i.MX6SX/UL */
300 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
301 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
302 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
303 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
304 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
305 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
306 /* LCFIF2_PODF on i.MX6SX */
307 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20)
308 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20
309 /* LCDIF_PIX_PODF on i.MX6SL */
310 #define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20)
311 #define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET 20
312 /* ACLK_EMI on i.MX6DQ/SDL/DQP */
313 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
314 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
315 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
316 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
317 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
318 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
319 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
320 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
321 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
322 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
323 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
324 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
325 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
326 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
327 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
328 /* QSPI1 exist on i.MX6SX/UL */
329 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
330 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
331 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
332 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
333 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
335 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
337 /* Define the bits in register CSCMR2 */
339 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
340 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
342 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
343 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
344 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
345 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
346 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
347 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
348 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
350 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
351 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
353 /* Define the bits in register CSCDR1 */
355 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
356 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
358 /* CSCDR1_GPMI/BCH exist on i.MX6UL */
359 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
360 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
361 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
362 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
364 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
365 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
366 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
367 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
368 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
369 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
370 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
371 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
373 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
374 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
375 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
376 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
378 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
379 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
380 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
381 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
383 /* Define the bits in register CS1CDR */
385 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22)
386 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22
387 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16)
388 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16
389 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6)
390 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6
391 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F
392 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0
394 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
395 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
396 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
397 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
398 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
399 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
400 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
401 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
402 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
403 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
404 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
405 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
407 /* Define the bits in register CS2CDR */
408 /* QSPI2 on i.MX6SX */
409 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
410 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
412 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
413 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
415 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
416 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
417 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
419 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
420 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
422 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
423 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
424 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
426 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
427 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
430 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
433 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
434 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
435 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
436 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
437 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
438 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
439 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
440 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
441 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
442 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
443 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
444 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
446 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
447 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
448 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
449 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
450 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
451 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
452 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
453 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
455 /* Define the bits in register CDCDR */
457 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
458 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
459 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
461 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
462 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
463 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
464 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
465 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
466 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
467 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
468 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
469 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
470 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
471 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
472 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
474 /* Define the bits in register CHSCCDR */
476 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
477 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
478 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
479 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
480 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
481 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
482 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
483 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
484 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
485 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
486 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
487 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
489 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
490 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
491 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
492 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
493 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
494 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
495 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
496 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
497 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
498 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
499 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
500 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
503 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15)
504 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15
505 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12)
506 #define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12
507 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9)
508 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9
510 #define CHSCCDR_CLK_SEL_LDB_DI0 3
511 #define CHSCCDR_PODF_DIVIDE_BY_3 2
512 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
514 /* Define the bits in register CSCDR2 */
515 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
516 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
517 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
518 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
519 /* LCDIF1 on i.MX6SX/UL */
520 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15)
521 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15
522 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12)
523 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12
524 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9)
525 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9
526 /* LCDIF2 on i.MX6SX */
527 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6)
528 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6
529 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3)
530 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3
531 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0)
532 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0
535 #define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6)
536 #define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 6
537 #define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3)
538 #define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET 3
540 /* All IPU2_DI1 are LCDIF1 on MX6SX */
541 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
542 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
543 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
544 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
545 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
546 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
547 /* All IPU2_DI0 are LCDIF2 on MX6SX */
548 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
549 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
550 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
551 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
552 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
553 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
555 /* Define the bits in register CSCDR3 */
556 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
557 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
558 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
559 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
560 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
561 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
562 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
563 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
566 #define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16)
567 #define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16
568 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14)
569 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14
571 /* Define the bits in register CDHIPR */
572 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
573 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
575 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
577 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
578 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
579 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
580 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
582 /* Define the bits in register CLPCR */
583 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
584 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
586 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
587 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
588 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
590 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
591 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
593 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
594 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
596 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
597 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
598 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
599 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
600 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
601 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
602 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
603 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
605 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
606 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
607 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
609 #define MXC_CCM_CLPCR_LPM_MASK 0x3
610 #define MXC_CCM_CLPCR_LPM_OFFSET 0
612 /* Define the bits in register CISR */
613 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
615 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
617 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
618 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
619 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
620 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
621 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
622 #define MXC_CCM_CISR_COSC_READY (1 << 6)
623 #define MXC_CCM_CISR_LRF_PLL 1
625 /* Define the bits in register CIMR */
626 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
628 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
630 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
631 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
632 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
633 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
634 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
635 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
636 #define MXC_CCM_CIMR_MASK_LRF_PLL 1
638 /* Define the bits in register CCOSR */
639 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
640 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
641 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
642 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
643 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
644 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
645 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
646 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
647 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
648 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
649 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
651 /* Define the bits in registers CGPR */
652 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
653 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
654 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
655 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
657 /* Define the bits in registers CCGRx */
658 #define MXC_CCM_CCGR_CG_MASK 3
661 #define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10
662 #define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET)
663 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12
664 #define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET)
666 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
667 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
668 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
669 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
670 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
671 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
672 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
673 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
674 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
675 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
676 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
677 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
678 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
679 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
680 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
681 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
682 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
683 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
684 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
685 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
686 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
687 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
688 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
689 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
690 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
691 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
692 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
693 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
695 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
696 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
698 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
699 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
702 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
703 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
704 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
705 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
706 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
707 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
708 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
709 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
710 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
711 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
712 /* CCGR1_ENET does not exist on i.MX6SX/UL */
713 #define MXC_CCM_CCGR1_ENET_OFFSET 10
714 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
715 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
716 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
717 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
718 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
719 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
720 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
722 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
723 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
725 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
726 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
727 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
728 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
730 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
731 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
733 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
734 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
736 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
737 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
738 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
739 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
742 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
743 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
745 #define MXC_CCM_CCGR2_CSI_OFFSET 2
746 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
749 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
750 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
752 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
753 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
754 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
755 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
756 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
757 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
758 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
759 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
760 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
761 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
762 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
763 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
764 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
765 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
766 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
767 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
768 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
769 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
770 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
771 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
772 /* i.MX6SX/UL LCD and PXP */
773 #define MXC_CCM_CCGR2_LCD_OFFSET 28
774 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
775 #define MXC_CCM_CCGR2_PXP_OFFSET 30
776 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
778 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
779 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
780 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
781 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
784 #define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0
785 #define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET)
786 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4
787 #define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET)
789 /* Exist on i.MX6SX */
790 #define MXC_CCM_CCGR3_M4_OFFSET 2
791 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
793 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4
794 #define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET)
795 #define MXC_CCM_CCGR3_ENET_OFFSET 4
796 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
797 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
798 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
801 #define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6
802 #define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
803 #define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8
804 #define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
806 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
807 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
808 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
809 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
810 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
811 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
813 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
814 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
815 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
816 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
817 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
818 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
819 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
820 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
822 /* QSPI1 exists on i.MX6SX/UL */
823 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
824 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
826 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
827 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
828 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
829 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
831 /* A7_CLKDIV/WDOG1 on i.MX6UL */
832 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
833 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
834 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
835 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
837 #define MXC_CCM_CCGR3_MLB_OFFSET 18
838 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
839 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
840 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
842 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
843 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
845 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
846 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
847 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
848 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
850 #define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6
851 #define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
852 #define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8
853 #define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
854 #define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10
855 #define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
857 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
858 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
859 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
860 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
862 /* GPIO4 on i.MX6UL/ULL */
863 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
864 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
867 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
868 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
872 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30
873 #define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET)
875 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
876 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
877 /* QSPI2 on i.MX6SX */
878 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
879 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
880 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
881 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
882 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
883 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
884 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
885 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
886 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
887 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
888 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
889 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
890 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
891 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
892 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
893 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
894 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
895 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
896 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
897 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
898 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
899 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
900 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
901 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
903 #define MXC_CCM_CCGR5_ROM_OFFSET 0
904 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
906 #define MXC_CCM_CCGR5_SATA_OFFSET 4
907 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
909 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
910 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
911 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
912 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
913 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
914 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
915 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
916 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
917 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
918 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
919 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
920 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
921 #define MXC_CCM_CCGR5_UART_OFFSET 24
922 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
923 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
924 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
926 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
927 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
928 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
929 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
932 /* PRG_CLK0 exists on i.MX6QP */
933 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24)
935 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
936 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
937 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
938 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
939 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
940 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
941 #define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6
942 #define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET)
943 #define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8
944 #define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET)
946 #define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8
947 #define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET)
948 /* GPMI/BCH on i.MX6UL */
949 #define MXC_CCM_CCGR6_BCH_OFFSET 6
950 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
951 #define MXC_CCM_CCGR6_GPMI_OFFSET 8
952 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
954 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
955 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
956 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
957 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
958 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
959 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
961 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18
962 #define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET)
963 /* The following *CCGR6* exist only i.MX6SX */
964 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
965 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
966 #define MXC_CCM_CCGR6_VADC_OFFSET 20
967 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
968 #define MXC_CCM_CCGR6_GIS_OFFSET 22
969 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
970 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
971 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
972 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
973 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
974 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
975 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
976 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
977 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
978 /* The two does not exist on i.MX6SX */
979 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
980 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
982 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
983 #define BP_ANADIG_PLL_SYS_RSVD0 20
984 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
985 #define BF_ANADIG_PLL_SYS_RSVD0(v) \
986 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
987 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
988 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
989 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
990 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
991 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
992 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
993 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
994 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
995 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
996 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
997 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
998 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
999 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
1000 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
1001 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
1002 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
1003 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
1004 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
1005 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
1006 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
1007 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
1008 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
1009 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
1011 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
1012 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
1013 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
1014 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
1015 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
1016 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
1017 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
1018 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
1019 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
1020 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
1021 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
1022 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
1023 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
1024 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
1025 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
1026 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
1027 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
1028 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
1029 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
1030 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
1031 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
1032 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
1033 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
1034 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
1035 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
1036 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
1037 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
1038 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
1039 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
1040 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
1041 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
1043 #define BM_ANADIG_PLL_528_LOCK 0x80000000
1044 #define BP_ANADIG_PLL_528_RSVD1 19
1045 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
1046 #define BF_ANADIG_PLL_528_RSVD1(v) \
1047 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
1048 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
1049 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
1050 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
1051 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
1052 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
1053 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
1054 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1055 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
1056 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
1057 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
1058 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
1059 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
1060 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
1061 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
1062 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
1063 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
1064 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
1065 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
1066 #define BP_ANADIG_PLL_528_RSVD0 1
1067 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
1068 #define BF_ANADIG_PLL_528_RSVD0(v) \
1069 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
1070 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
1072 #define BP_ANADIG_PLL_528_SS_STOP 16
1073 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
1074 #define BF_ANADIG_PLL_528_SS_STOP(v) \
1075 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
1076 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
1077 #define BP_ANADIG_PLL_528_SS_STEP 0
1078 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
1079 #define BF_ANADIG_PLL_528_SS_STEP(v) \
1080 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1082 #define BP_ANADIG_PLL_528_NUM_RSVD0 30
1083 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
1084 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
1085 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
1086 #define BP_ANADIG_PLL_528_NUM_A 0
1087 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
1088 #define BF_ANADIG_PLL_528_NUM_A(v) \
1089 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1091 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
1092 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
1093 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
1094 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
1095 #define BP_ANADIG_PLL_528_DENOM_B 0
1096 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
1097 #define BF_ANADIG_PLL_528_DENOM_B(v) \
1098 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1100 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
1101 #define BP_ANADIG_PLL_AUDIO_RSVD0 22
1102 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
1103 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
1104 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
1105 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
1106 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
1107 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
1108 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
1109 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1110 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
1111 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
1112 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
1113 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
1114 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
1115 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
1116 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1117 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
1118 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1119 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1120 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
1121 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
1122 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
1123 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
1124 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
1125 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
1126 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
1127 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
1128 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
1129 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
1130 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
1131 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1133 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
1134 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
1135 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
1136 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
1137 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
1138 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
1139 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
1140 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1142 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
1143 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
1144 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
1145 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
1146 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
1147 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
1148 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
1149 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1151 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
1152 #define BP_ANADIG_PLL_VIDEO_RSVD0 22
1153 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
1154 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
1155 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
1156 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
1157 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
1158 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
1159 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
1160 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1161 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
1162 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
1163 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
1164 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
1165 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
1166 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
1167 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1168 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
1169 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1170 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1171 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
1172 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
1173 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
1174 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
1175 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
1176 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
1177 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
1178 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
1179 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
1180 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
1181 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
1182 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1184 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
1185 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
1186 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
1187 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
1188 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
1189 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
1190 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
1191 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1193 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
1194 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
1195 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
1196 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
1197 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
1198 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
1199 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
1200 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1202 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
1203 #define BP_ANADIG_PLL_ENET_RSVD1 21
1204 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
1205 #define BF_ANADIG_PLL_ENET_RSVD1(v) \
1206 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
1207 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
1208 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
1209 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
1210 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
1211 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
1212 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
1213 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
1214 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
1215 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
1216 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1217 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1218 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1219 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1220 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1221 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
1222 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
1223 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1224 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1225 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1226 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1227 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1228 #define BP_ANADIG_PLL_ENET_RSVD0 2
1229 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1230 #define BF_ANADIG_PLL_ENET_RSVD0(v) \
1231 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1232 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1233 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1234 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1235 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1237 /* ENET2 for i.MX6SX/UL */
1238 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
1239 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
1240 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \
1241 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
1243 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1244 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1245 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1246 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1247 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1248 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1249 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1250 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1251 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1252 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1253 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1254 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1255 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1256 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1257 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1258 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1259 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1260 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1261 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1262 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1263 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1264 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1265 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1266 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1268 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1269 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1270 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1271 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1272 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1273 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1274 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1275 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1276 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1277 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1278 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1279 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1280 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1281 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1282 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1283 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1284 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1285 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1286 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1287 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1288 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1289 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1290 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1291 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1293 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
1294 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
1295 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
1297 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
1298 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23
1300 #define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
1301 #define BP_PMU_MISC2_AUDIO_DIV_LSB 15
1303 #define PMU_MISC2_AUDIO_DIV(v) \
1304 (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
1305 (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
1306 ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
1307 BP_PMU_MISC2_AUDIO_DIV_LSB))
1309 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */