2 * (C) Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
24 #define __ASM_ARCH_MX5_IMX_REGS_H__
26 #if defined(CONFIG_MX51)
27 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
28 #define IPU_CTRL_BASE_ADDR 0x40000000
29 #define SPBA0_BASE_ADDR 0x70000000
30 #define AIPS1_BASE_ADDR 0x73F00000
31 #define AIPS2_BASE_ADDR 0x83F00000
32 #define CSD0_BASE_ADDR 0x90000000
33 #define CSD1_BASE_ADDR 0xA0000000
34 #define NFC_BASE_ADDR_AXI 0xCFFF0000
35 #elif defined(CONFIG_MX53)
36 #define IPU_CTRL_BASE_ADDR 0x18000000
37 #define SPBA0_BASE_ADDR 0x50000000
38 #define AIPS1_BASE_ADDR 0x53F00000
39 #define AIPS2_BASE_ADDR 0x63F00000
40 #define CSD0_BASE_ADDR 0x70000000
41 #define CSD1_BASE_ADDR 0xB0000000
42 #define NFC_BASE_ADDR_AXI 0xF7FF0000
43 #define IRAM_BASE_ADDR 0xF8000000
45 #error "CPU_TYPE not defined"
48 #define IRAM_SIZE 0x00020000 /* 128 KB */
51 * SPBA global module enabled #0
53 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
54 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
55 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
56 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
57 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
58 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
59 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
60 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
61 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
62 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
63 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
64 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
69 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
70 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
71 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
72 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
73 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
74 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
75 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
76 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
77 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
78 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
79 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
80 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
81 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
82 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
83 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
84 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
85 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
86 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
87 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
88 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
90 #if defined(CONFIG_MX53)
91 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
92 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
93 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
98 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
99 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
100 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
101 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
102 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
103 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
104 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
105 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
106 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
107 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
108 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
109 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
110 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
111 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
112 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
113 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
114 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
115 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
116 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
117 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
118 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
119 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
120 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
121 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
122 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
123 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
124 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
125 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
126 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
127 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
128 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
129 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
132 * Number of GPIO pins per port
134 #define GPIO_NUM_PIN 32
136 #define IIM_SREV 0x24
137 #define ROM_SI_REV 0x48
139 #define NFC_BUF_SIZE 0x1000
142 #define M4IF_FBPM0 0x40
143 #define M4IF_FIDBP 0x48
145 /* Assuming 24MHz input clock with doubler ON */
147 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
148 #define DP_MFD_850 (48 - 1)
149 #define DP_MFN_850 41
151 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
152 #define DP_MFD_800 (3 - 1)
155 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
156 #define DP_MFD_700 (24 - 1)
159 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
160 #define DP_MFD_665 (96 - 1)
161 #define DP_MFN_665 89
163 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
164 #define DP_MFD_532 (24 - 1)
165 #define DP_MFN_532 13
167 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
168 #define DP_MFD_400 (3 - 1)
171 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
172 #define DP_MFD_216 (4 - 1)
175 #define CHIP_REV_1_0 0x10
176 #define CHIP_REV_1_1 0x11
177 #define CHIP_REV_2_0 0x20
178 #define CHIP_REV_2_5 0x25
179 #define CHIP_REV_3_0 0x30
181 #define BOARD_REV_1_0 0x0
182 #define BOARD_REV_2_0 0x1
184 #define IMX_IIM_BASE (IIM_BASE_ADDR)
186 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
187 #include <asm/types.h>
189 extern void imx_get_mac_from_fuse(unsigned char *mac);
191 #define __REG(x) (*((volatile u32 *)(x)))
192 #define __REG16(x) (*((volatile u16 *)(x)))
193 #define __REG8(x) (*((volatile u8 *)(x)))
249 /* System Reset Controller (SRC) */
294 struct fuse_bank1_regs {
300 #endif /* __ASSEMBLER__*/
302 #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */